The AES can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample Xilinx results with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

AES Standard Core Xilinx Implementation Results

Family

LUTs

BRAMs

Freq.
(MHz)

Throughout (Mbps)

Virtex-7 (-3)
621
0
300
873
Kintex-7 (-2)
567
0
150
436
Kintex UltraScale (-2)
606
0
250
727

Throughput for a 128-bit key size

AES Fast Core Xilinx Implementation Results

Family

LUTs

BRAMs

Freq.
(MHz)

Throughout (Mbps)

Virtex-7 (-3)
2,110
0
200
2,327
Kintex-7 (-2)
2,097
0
150
1,745
Kintex UltraScale (-2)
2,236
0
250
2,090

Throughput for a 128-bit key size

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