The AES can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample ASIC pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

AES Standard Core ASIC Implementation Results

ASIC Technology

Number of
eq. gates

Fmax
(MHz)

Throughout (Gbps)

TSMC 16nm
6,736
500
1.455
TSMC 28nm HPM
7,058
500
1.455

TSMC 40nm G

8,971
500
1.455

Throughput for a 128-bit key size

AES Fast Core ASIC Implementation Results

ASIC Technology

Number of
eq. gates

Fmax
(MHz)

Throughout (Gbps)

TSMC 16nm
23,715
500
5.818
TSMC 28nm HPM
25,082
500
5.818

TSMC 40nm G

32,874
500
5.818

Throughput for a 128-bit key size

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