The AES can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample Intel results with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

AES Standard Core Intel Implementation Results

Family

ALMs

RAM bits

Freq.
(MHz)

Throughout (Mbps)

Arria 10 GX (-2)
588
32
100
291
Stratix V (-1)
612
0
150
436
MAX 10 (-7)
2,024
16
75
218

Throughput for a 128-bit key size for ECB mode

AES Fast Core Intel Implementation Results

Family

ALMs

RAM bits

Freq.
(MHz)

Throughout (Mbps)

Arria 10 GX (-2)
2,124
0
100
1,164
Stratix V (-1)
2,423
0
150
1,745
MAX 10 (-7)
7,777
0
50
582

Throughput for a 128-bit key size for ECB mode

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