Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG LS
Encoder
Lossless & Near-Lossless

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • Intel Accelerator
    • Xiinx PCIe Board

Companion Cores
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
RTP Stack for H.264
RTP Stack for JPEG
• MPEG Transport Stream
  Encapsulator

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
40G UDPIP Stack
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN PHY Daughter Card
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
IEEE 802.1AS Hardware
   Protocol Stack

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

  • Encrypts and decrypts using the AES Rijndael Block Cipher Algorithm
  • Implemented according to the IEEE P1619™/D16 standard
  • Capable of processing 128 bits/cycle
  • Employs user-programmable key size of 128 or 256 bits
  • Two architectural versions:
    • High throughput version can process 128 bits/cycle
    • Higher throughput version can process 256 bits/cycle
  • Arbitrary IV length
  • Works with the integrated key expansion function
  • Simple, fully synchronous, reusable design
  • Available as fully functional and synthesizable VHDL or Verilog, or as a netlist for popular programmable devices
  • Complete deliverables include test benches, C model and test vector generator

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

Compare
Versions

  • AES Advanced Encryption Standard Core
  • AES-P Programmable Advanced Encryption Standard Core
  • AES-CCM Advanced Encryption Standard Core
  • AES-GCM AES GCM Authenticated Encrypt/Decrypt Core
  • KEXP Key Expander Core

AES Core Links

NIST: Approved Block Ciphers

FIPS 197, Advanced Encryption Standard (AES): download PDF

AES test suite: The Advanced Encryption Standard Algorithm Validation Suite (AESAVS): download PDF

White Paper

AES Encryption and CAST’s AES IP Cores (PDF)

AES-XTS Advanced Encryption Standard Core

The AES-XTS encryption IP core implements encryption/decryption for sector-based storage data. It uses the AES block cypher, in compliance with the NIST Advanced Encryption Standard, as a subroutine.  The core processes 128 bits per cycle, and is programmable for 128- and 256-bit key lengths.

Two architectural versions are available to suit system requirements. The High Throughout version (AES-X) is more compact can process 128 bits/cycle.  The Higher Throughput version (AES-X2) can process 256 bits/cycle.

The AES-XTS core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.

The AES-XTS core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.

AES-XTS reference designs have been evaluated in a variety of technologies. See representative implementation results (in a new pop-up window):

ASIC numbers Altera numbers Xilinx numbers

Block Diagram

aes-XTS block diagram

Related Products

AES in ECB, CFB, CBC, OFB, CTR, CCM, GCM and LRW modes are also available as stand-alone cores.

AES-P: run-time programmable AES core supporting ECB, CFB, CBC, OFB, and CTR modes.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products, and is proven in FPGA technologies.

Export Permits

This core implements encryption functions and as such it is subject to export control regulations. Export to your country may or may not require a special export license. Please contact CAST to determine what applies in your specific case.

Deliverables

The core is available in ASIC (RTL) or FPGA (netlist) forms, and includes everything required for successful implementation. The ASIC version includes

Comparing AES Encryption/Decryption Cores

  AES* (-S or -F) AES-P (-S or -F) AES-GCM or AES-CCM
(-S or -F)
AES-GCM, AES-CCM or AES-XTS
(-X or -X2)
Run time Programmable Encryption or Decryption operation yes yes yes yes
Run-time Programmagle Cipher-Key length yes yes yes yes
Run-time Programmable Block Cipher mode no yes no no
ECB mode yes yes no no
CBC mode yes yes no no
CFB mode yes yes no no
OFB mode yes yes no no
CTR mode yes yes no no
LRW mode yes no no no
Key Expander optional optional optional yes
Number of bits/cycle for128/192/256 key 2.91/2.46/2.13 or
11.64/9.85/8.53
2.91/2.46/2.13 or
11.64/9.85/8.53
2.91/2.46/2.13 or
11.64/9.85/8.53
128/128/128 or
256/256/256

* only one encryption/deceryption mode supported by each release of the core

 

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