- Encrypts and decrypts using the AES Rijndael Block Cipher Algorithm
- Implemented according to the IEEE P1619™/D16 standard
- Capable of processing 128 bits/cycle
- Employs user-programmable key size of 128 or 256 bits
- Two architectural versions:
- High throughput version can process 128 bits/cycle
- Higher throughput version can process 256 bits/cycle
- Arbitrary IV length
- Works with the integrated key expansion function
- Simple, fully synchronous, reusable design
- Available as fully functional and synthesizable VHDL or Verilog, or as a netlist for popular programmable devices
- Complete deliverables include test benches, C model and test vector generator
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- AES Advanced Encryption Standard Core
- AES-P Programmable Advanced Encryption Standard Core
- AES-CCM Advanced Encryption Standard Core
- AES-GCM AES GCM Authenticated Encrypt/Decrypt Core
- KEXP Key Expander Core
AES Core Links
FIPS 197, Advanced Encryption Standard (AES): download PDF
AES test suite: The Advanced Encryption Standard Algorithm Validation Suite (AESAVS): download PDF
AES-XTS Advanced Encryption Standard Core
The AES-XTS encryption IP core implements encryption/decryption for sector-based storage data. It uses the AES block cypher, in compliance with the NIST Advanced Encryption Standard, as a subroutine. The core processes 128 bits per cycle, and is programmable for 128- and 256-bit key lengths.
Two architectural versions are available to suit system requirements. The High Throughout version (AES-X) is more compact can process 128 bits/cycle. The Higher Throughput version (AES-X2) can process 256 bits/cycle.
The AES-XTS core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.
AES in ECB, CFB, CBC, OFB, CTR, CCM, GCM and LRW modes are also available as stand-alone cores.
AES-P: run-time programmable AES core supporting ECB, CFB, CBC, OFB, and CTR modes.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products, and is proven in FPGA technologies.
This core implements encryption functions and as such it is subject to export control regulations. Export to your country may or may not require a special export license. Please contact CAST to determine what applies in your specific case.
The core is available in ASIC (RTL) or FPGA (netlist) forms, and includes everything required for successful implementation. The ASIC version includes
- HDL RTL source code
Sophisticated HDL Testbench (self checking)
C Model & test vector generator
Simulation script, vectors & expected results
Comparing AES Encryption/Decryption Cores
|AES* (-S or -F)||AES-P (-S or -F)||
AES-GCM or AES-CCM
(-S or -F)
|AES-GCM, AES-CCM or AES-XTS
(-X or -X2)
|Run time Programmable Encryption or Decryption operation||yes||yes||yes||yes|
|Run-time Programmagle Cipher-Key length||yes||yes||yes||yes|
|Run-time Programmable Block Cipher mode||no||yes||no||no|
|Number of bits/cycle for128/192/256 key||2.91/2.46/2.13 or
* only one encryption/deceryption mode supported by each release of the core