The AES-XTS can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample Xilinx results with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

AES-XTS High Throughput (-X) Xilinx Implementation Results

Family

LUTs

BRAMs

Freq.
(MHz)

Throughout (Gbps)

Virtex-7 (-3)
4,089
116
225
 28.8
Virtex UltraScale (-3)
4,054
116.5
300
38.4
Kintex UltraScale (-3)
4,065
116.5
325
41.6
Kintex UltraScale (-1)
4,242
116.5
200
25.6
Kintex UltraScale+ (-1)
4,180
116
250
32.0
Kintex UltraScale+ (-3)
4,052
116.5
325
 41.6

AES-XTS Higher Throughput (-X2) Xilinx Implementation Results

Family

LUTs

BRAMs

Freq.
(MHz)

Throughout (Gbps)

Virtex-7 (-3)
6,941
224
200
 51.2
Virtex UltraScale (-3)
6,801
224.5
275
70.4
Kintex UltraScale (-3)
6,894
224.5
325
83.2
Kintex UltraScale (-1)
7,317
224
200
51.2
Kintex UltraScale+ (-1)
7,286
224.5
250
64.0
Kintex UltraScale+ (-3)
6,894
224.5
325
83.2

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