The AES-XTS can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample ASIC pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

AES-XTS High Throughput (-X)  ASIC Implementation Results

ASIC Technology

Number of
eq. gates

Fmax
(MHz)

Throughout (Gbps)

TSMC 40nm
743,552
800
102.40
TSMC 28nm
513,767
800
102.40
TSMC 16nm
365,886
800
102.40

AES-XTS Higher Throughput (-X2) ASIC Implementation Results

ASIC Technology

Number of
eq. gates

Fmax
(MHz)

Throughout (Gbps)

TSMC 40nm
1,462,314
800
102.40
TSMC 28nm
1,042,408
800
102.40
TSMC 16nm
 715,858
800
102.40

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