The AES-XTS can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample Intel results with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

AES-XTS High Throughput (-X)  Intel Implementation Results

Family

ALMs

RAM bits

Freq.
(MHz)

Throughout (Gbps)

Arria 10 GX (-1)
4,674
1,843,200
170
 21.76
Stratix V (-1)
4,831
1,843,200
210
 26.88

AES-XTS Higher Throughput (-X2) Intel Implementation Results

Family

ALMs

RAM bits

Freq.
(MHz)

Throughout (Gbps)

Arria 10 GX (-1)
8,526
3,547,136
150
 38.40
Stratix V (-1)
8,921
3,547,136
180
  46.08

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