AES-P Programmable Advanced Encryption Standard Core

The AES-P encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths.

Two architectural versions are available to suit system requirements. The Standard version (AES32-P) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES128-P) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block.  It can be programmed to use any of the following cypher modes: ECB, CBC, OFB, CFB and CTR.

The core works with a pre-expanded key, or with optional key expansion logic.

The AES-P core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.

AES-P reference designs have been evaluated in a variety of technologies. See representative implementation results (in a new pop-up window):

Applications

The AES-P can be utilized for a variety of encryption applications including:

• Protected network routers
  
• Electronic financial transactions
  
• Secure wireless communications
  
• Secure video surveillance systems
  
• Encrypted data storage

Block Diagram

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products, and is proven in FPGA technologies.

Export Permits

This core is approved for export to any country, except for the following:

Cuba Iran Iraq Libya

North Korea Sudan Syria

It is the customer’s responsibility to check with relevant authorities regarding the re-export of equipment containing the AES technology.

Deliverables

The core is available in ASIC (RTLL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)

• Sophisticated HDL Testbench (self checking)
  

• C Model & test vector generator
  

• Simulation script, vectors & expected results
  

• Synthesis script
  

• User documentation

Comparing AES Encryption/Decryption Cores

	AES*	AES-P	AES-GCM	AES-CCM
Run time Programmable Encryption or Decryption operation	yes	yes	yes	yes
Run-time Programmagle Cipher-Key length	yes	yes	yes	yes
Run-time Programmable Block Cipher mode	no	yes	no	no
ECB mode	yes	yes	no	no
CBC mode	yes	yes	no	no
CFB mode	yes	yes	no	no
OFB mode	yes	yes	no	no
CTR mode	yes	yes	no	no
LRW mode	yes	no	no	no
Key Expander	optional	optional	optional	optional
Number of cycles per data block 128/192/256 key	44/52/60 or 11/13/15	44/52/60 or 11/13/15	44/52/60 or 11/13/15	44/52/60 or 11/13/15
* only one encryption/deceryption mode supported by each release of the core