The AES-P can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample Xilinx results with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

AES-P Standard Core Xilinx Implementation Results

Family

LUTs

BRAMs

Freq.
(MHz)

Throughout (Mbps)

Virtex-7 (-3)
822
0
250
727
Kintex-7 (-2)
779
0
200
582
Kintex UltraScale (-1)
394
2
200
582
Kintex UltraScale (-2)
795
0
200
582
Kintex UltraScale+ (-1)
394
2
400
1,164

Throughput for a 128-bit key size

AES-P Fast Core Xilinx Implementation Results

Family

LUTs

BRAMs

Freq.
(MHz)

Throughout (Mbps)

Virtex-7 (-3)
2,445
0
200
2,327
Kintex UltraScale (-1)
1,033
8
200
2,327
Kintex UltraScale (-2)
2,460
0
200
2,327
Kintex UltraScale+ (-1)
1,041
8
350
4,072

Throughput for a 128-bit key size

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