The AES-P can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample Intel results with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

AES-P Standard Core Intel Implementation Results

Family

ALMs

RAM bits

Freq.
(MHz)

Throughout (Mbps)

Arria 10 GX (-2)
756
32
80
233
Stratix V (-1)
735
0
100
291
MAX 10 (-7)
2,421
16
50
145

Throughput for a 128-bit key size

AES-P Fast Core Intel Implementation Results

Family

ALMs

RAM bits

Freq.
(MHz)

Throughout (Mbps)

Arria 10 GX (-2)
2,679
0
80
931
Stratix V (-1)
2,763
0
100
1,164
MAX 10 (-7)
8,432
0
50
582

Throughput for a 128-bit key size

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