Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
16450S, 16550S, 16750S

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream

Octal SPI
Quad SPI
Single SPI
SPI to AHB-Lite

Data Link Controllers
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES, programmable
Key Expander

DES single
DES triple

Hash Functions
SHA-3 (Keccak)

  • Encrypts and decrypts using the AES Rijndael Block Cipher Algorithm
  • Satisfies Federal Information Processing Standard (FIPS) Publication 197 from the US National Institute of Standards and Technology (NIST)
  • Processes 128-bit data in 32-bit blocks
  • Employs user-programmable key size of 128, 192, or 256 bits
  • Two architectural versions:
    • Standard is more compact: 32-bit data path size
      Processes each 128-bit data block in 44/52/60 clock cycles for 128/192/256-bit cipher keys, respectively
    • Fast yields higher transmission rates: 128-bit data path
      Processes each 128-bit block in 11/13/15 clock cycles for 128/192/256-bit cipher keys, respectively
  • Arbitrary IV length for fast version
  • Works with a pre-expended key or can integrate the optional key expansion function
  • Simple, fully synchronous, reusable design
  • Available as fully functional and synthesizable VHDL or Verilog, or as a netlist for popular programmable devices
  • Complete deliverables include test benches, C model and test vector generator

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products


  • AES Advanced Encryption Standard Core
  • AES-P Programmable Advanced Encryption Standard Core
  • AES-CCM AES CCM Advanced Encryption Standard Core
  • KEXP Key Expander Core

AES Core Links

NIST: Approved Block Ciphers

FIPS 197, Advanced Encryption Standard (AES): download PDF

AES test suite: The Advanced Encryption Standard Algorithm Validation Suite (AESAVS): download PDF

White Paper

AES Encryption and CAST’s AES IP Cores (PDF)

AES-GCM AES-GCM Authenticated Encrypt/Decrypt Core

The AES-GCM encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths.

Two architectural versions are available to suit system requirements. The Standard version (AES32) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES128) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block.

GCM stands for Galois Counter. GCM is a generic authenticate-and-encrypt block cipher mode. A Galois Field (GF) multiplier/accumulator is utilized to generate an authentication tag while CTR (Counter) mode is used to encrypt.

The AES-GCM core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.

AES-GCM reference designs have been evaluated in a variety of technologies. See representative implementation results (in a new pop-up window):

ASIC numbers Altera numbers Xilinx numbers


The AES-GCM can be utilized for a variety of encryption applications including:

Block Diagram

aes-gcm block diagram


The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.


The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products, and is proven in FPGA technologies.

Export Permits

This core is approved for export to any country, except for the following:

  • Cuba
  • Iran
  • Iraq
  • Libya
  • North Korea
  • Sudan
  • Syria

It is the customer’s responsibility to check with relevant authorities regarding the re-export of equipment containing the AES technology.


The AES-GCM is available as a soft core (synthesizable HDL) for ASIC technologies and as a firm core (netlist) for FPGA technologies, and includes everything required for successful implementation. The ASIC version includes:

Comparing AES Encryption/Decryption Cores

Run time Programmable Encryption or Decryption operation yes yes yes yes
Run-time Programmagle Cipher-Key length yes yes yes yes
Run-time Programmable Block Cipher mode no yes no no
ECB mode yes yes no no
CBC mode yes yes no no
CFB mode yes yes no no
OFB mode yes yes no no
CTR mode yes yes no no
LRW mode yes no no no
Key Expander optional optional optional optional
Number of cycles per data block 128/192/256 key 44/52/60 or 11/13/15 44/52/60 or 11/13/15 44/52/60 or 11/13/15 44/52/60 or 11/13/15

* only one encryption/deceryption mode supported by each release of the core


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