The AES-GCM can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample Xilinx results with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core.Please contact CAST to get characterization data for your target configuration and technology.

AES-GCM Standard Core Xilinx Implementation Results

Family

LUTs

BRAMs

Freq.
(MHz)

Throughout (Mbps)

Virtex-7 (-3)
1,098
0
200
582
Kintex-7 (-2)
1,063
0
150
436
Kintex UltraScale (-1)
920
2
200
582
Kintex UltraScale (-2)
1,108
0
200
582
Kintex UltraScale+ (-1)
930
2
400
1,164

Throughput for a 128-bit key size

AES-GCM Fast Core Xilinx Implementation Results

Family

LUTs

BRAMs

Freq.
(MHz)

Throughout (Mbps)

Virtex-7 (-3)
2,486
0
300
3,491
Kintex UltraScale (-1)
2,172
8
250
2,908
Kintex UltraScale+ (-1)
2,169
8
350
4,071

Throughput for a 128-bit key size

AES-GCM High Throughput (-X)  Xilinx Implementation Results

Family

LUTs

BRAMs

Freq.
(MHz)

Throughout (Gbps)

Virtex-7 (-3)
9,348
108
200
 25.6
Virtex UltraScale (-3)
9,651
108
300
38.4
Kintex UltraScale (-1)
11,619
108
200
25.6
Kintex UltraScale+ (-1)
11,612
108
300
38.4
Kintex UltraScale+ (-3)
11,624
108
400
 51.2

AES-GCM Higher Throughput (-X2)  Xilinx Implementation Results

Family

LUTs

BRAMs

Freq.
(MHz)

Throughout (Gbps)

Virtex-7 (-3)
25,246
216
200
51.2
Virtex UltraScale (-3)
25,194
216
250
  64.0
Kintex UltraScale (-1)
28,612
216
200
51.2
Kintex UltraScale+ (-1)
28,618
216
250
64.0
Kintex UltraScale+ (-3)
25,279
216
350
89.6

 

close window