The AES-GCM can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample ASIC pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

AES-GCM Standard Core ASIC Implementation Results

ASIC Technology

Number of
eq. gates

Fmax
(MHz)

Throughput (Gbps)

TSMC 16nm
10,556
500
1.455
TSMC 28nm HPM
11,041
500
1.455

TSMC 40nm G

14.993
500
1.455

Throughput for a 128-bit key size

AES-GCM Fast Core ASIC Implementation Results

ASIC Technology

Number of
eq. gates

Fmax
(MHz)

Throughput (Gbps)

TSMC 16nm
21,909
500
5.818
TSMC 28nm HPM
21,368
500
5.818
TSMC 40nm G
26,659
500
5.818

Throughput for a 128-bit key size

AES-GCM High Throughput (-X) ASIC Implementation Results

ASIC Technology

Number of
eq. gates

Fmax
(MHz)

Throughput (Gbps)

TSMC 40nm
384,786
800
102.40
TSMC 28nm
270,39
800
102.40
TSMC 16nm
233,200
800
102.40

AES-GCM Higher Throughput (-X2) ASIC Implementation Results

ASIC Technology

Number of
eq. gates

Fmax
(MHz)

Throughput (Gbps)

TSMC 40nm
760,757
800
102.40
TSMC 28nm
532,089
800
102.40
TSMC 16nm
451,539
800
102.40

 

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