The AES-CCM can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample Xilinx results with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

AES-CCM Standard Core Xilinx Implementation Results

Family

LUTs

BRAMs

Freq.
(MHz)

Throughout (Mbps)

Virtex-7 (-3)
681
0
300
873
Kintex-7 (-2)
664
0
150
436
Kintex UltraScale+ (-1)
458
2
200
582
Kintex UltraScale (-2)
672
0
250
727
Kintex UltraScale+ (-1)
457
2
400
1,164

Throughput for a 128-bit key size

AES-CCM Fast Core Xilinx Implementation Results

Family

LUTs

BRAMs

Freq.
(MHz)

Throughout (Mbps)

Virtex-7 (-3)
1,478
0
300
3,491
Kintex UltraScale (-1)
812
8
200
2,326
Kintex UltraScale (-2)
1,460
0
250
2,908
Kintex UltraScale+ (-1)
832
8
400
4,652

Throughput for a 128-bit key size

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