32025 DSP IP Core C32025TX 16-bit Fixed-Point Digital Signal Processor Core

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Descripttion | Support | Verification | Deliverables

The C32025TX is a single-chip, high performance 16-bit fixed-point digital signal processor core. It implements the same instruction set as the TMS320C25 and provides the same interrupts, serial interface and timer, executing most of instructions in a single clock cycle.

The C32025TX is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with both-edge clocking, a synchronous reset, and no internal tri-states.

See representative implementation results (each in a new pop-up window):

Features

• Control Unit
• Single-clock per machine cycle operation
• 16-bit instruction decoding
• Repeat instructions for efficient use of program space
• 8-level Hardware Stack
• Central Arithmetic-Logic Unit
• 16-bit sign-extended parallel shifter
• 32-bit arithmetic and logical operations
• 16 x 16 bit parallel multiplier with a 32-bit product
• 32-bit accumulator with output shifter
• Single-cycle Multiply-and-Accumulate instructions
• Auxiliary Registers
• 8 x 16-bit registers for indirect addressing or data storage
• 16-bit Auxiliary Register Arithmetic Unit including operations with reversed-carry propagation
• 16-bit reload timer
• Memory addressing modes
• Direct – using a 9-bit Page Pointer and 7 LSBs of instruction word
• Indirect – using Auxiliary Register File
• Immediate – less than 16-bit via instruction word or full 16-bit long immediate following the instruction word
• Block moves for data/program management
• Interrupt Controller
• 6 interrupt sources plus reset and one software interrupt
• Synchronous serial port for direct codec interface
• Program Memory organization
• 4K-words of internal ROM
• Internal 256-word RAM block configurable either as program or data space
• 64K-word external program space
• Data Memory organization
• 2 Internal 256-word and one 32-word RAM blocks
• 64K-words of external data space
• 6 memory mapped registers
• 16 Input and 16 Output channels
• Wait states for interfacing slower off-chip devices
• Configurable synchronous/asynchronous external / internal memory support
• Power Management Unit for low-power operation
• Concurrent DMA using an extended Hold operation
• Multiprocessing support
• Global data memory interface

Applications

The C32025TX core is suitable for implementing a wide range of digital signal processing applications such as:

• Digital sound processing (adaptive filtering, FFT, other special sound effects)
• Voice recognition
• Telecommunications (modems, codecs)
• Medical equipment (diagnostics tools)
• Computers peripherals
• Various embedded data-intensive systems
  

Block Diagram

Functional Description

The architecture of the C32025TX ensures overall system speed and flexibility in processor configurations. The instruction set and control signals provide block memory transfers, communication to slower off-chip devices and multiproces-sing implementations. Single-clock multiply/accumulate instructions, two large on-chip RAM blocks, eight auxiliary registers with dedicated arithmetic unit, serial interface and hardware timer make the processor appropriate for data-intensive signal processing.

The C32025TX implements Harvard-type architecture to maximize processing power by maintaining two separate program and data buses for full-speed execution. The program bus carries instructions and immediate operands while data bus interconnects various components and carries data from/to any data memory space. Both buses can carry data for single-clock multiply & accumulate operations.

Instruction flow consists of three pipeline stages, essentially invisible to the user. The pre-fetch, decode and execute stages are independent, which allows instructions to overlap. Thus, three different instructions can be active during any given cycle.

Most instructions can be used in repeat mode, when they are executed a given number of times. This feature is most useful with block moves, multiply/accumulates, I/O transfers and table read/writes.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements. It has also been successfully implemented in commercial and prototype systems..

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Example design showing how to connect memories
• Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide

 

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Descripttion | Support | Verification | Deliverables

Download PDF datasheets for more info: ASIC | Altera | Lattice | Xilinx