Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

Processor Peripherals
AHB 32-bit DMA
AMBA Infrastructure Cores

Legacy Processors
See Legacy Cores >

These video and image compression cores help you handle video compression for demanding, high-quality applications or choose the best type of image compression for your specific system.

JPEG 2000
Encoder
J2K Platform

Block/Raster Converters
block-to-raster
raster-to-block
raster-block bidirect

Lossless Compression
LJPEG Encoder
LJPEG Decoder
JPEG-LS Encoder

Functions & Converters
Color Space Converter

Video Deinterlacers
Basic

Quickly complete the standrd parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores. Choose high-speed DisplayPort or PCI Express, Ethernet MACs, the CAN bus for automotive systems, and more.

High-Speed Serial
PCI Express
Family Overview
x1/x4
x8
application interface

Parallel
ECP slave
ATA/IDE interface

PCI — Target
32-bit
32-bit multi
64-bit
PCI — Master
32-bit
32-bit multi
64-bit
PCI — Host Bridge
32 bit
32 bit - AHB
32 bit & device - AHB

TCP/IP Stacks
UDP/IP stack

Ethernet MAC
Device Controllers

10/100
10/100 lite
Gigabit
Gigabit lite
Gigabit PCS

MAC Platforms
MAC/PCI

Customers find these cores to be an excellent solution for preserving existing product board designs when critical chips are no longer available for purchase.

 
80186XL
80186EC
80188EC
80251
387L math

DSPs
32025 16-bit
32025TX 16-bit

 

 

Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Cores for integrating security, controlling devices and displays, and other SoC functions.

Device Controllers
smart card reader

IR Remote Controls
RC5
NEC

Audio Interfaces
I2S-SC
I2S-MC
SPDIF

  • Control Unit
    • Single-clock per machine cycle operation
    • 16-bit instruction decoding
    • Repeat instructions for efficient use of program space
    • 8-level Hardware Stack
  • Central Arithmetic-Logic Unit
    • 16-bit sign-extended parallel shifter
    • 32-bit arithmetic and logical operations
    • 16 x 16 bit parallel multiplier with a 32-bit product
    • 32-bit accumulator with output shifter
    • Single-cycle Multiply-and-Accumulate instructions
  • Auxiliary Registers
    • 8 x 16-bit registers for indirect addressing or data storage
    • 16-bit Auxiliary Register Arithmetic Unit including operations with reversed-carry propagation
  • 16-bit reload timer
  • Memory addressing modes
    • Direct – using a 9-bit Page Pointer and 7 LSBs of instruction word
    • Indirect – using Auxiliary Register File
    • Immediate – less than 16-bit via instruction word or full 16-bit long immediate following the instruction word
    • Block moves for data/program management
  • Interrupt Controller
    • 6 interrupt sources plus reset and one software interrupt
  • Synchronous serial port for direct codec interface
  • Program Memory organization
    • 4K-words of internal ROM
    • Internal 256-word RAM block configurable either as program or data space
    • 64K-word external program space
  • Data Memory organization
    • 2 Internal 256-word and one 32-word RAM blocks
    • 64K-words of external data space
    • 6 memory mapped registers
  • 16 Input and 16 Output channels
  • Wait states for interfacing slower off-chip devices
  • Configurable synchronous/asynchronous external / internal memory support
  • Power Management Unit for low-power operation
  • Concurrent DMA using an extended Hold operation
  • Multiprocessing support
  • Global data memory interface

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PDF Datasheets

ASIC
Altera, Lattice, Xilinx

Related Products

  • C32025 16-bit Digital Signal Processor (DSP)

32025 DSP IP Core C32025TX 16-bit Fixed-Point Digital Signal Processor Core

The C32025TX is a single-chip, high performance 16-bit fixed-point digital signal processor core. It implements the same instruction set as the TMS320C25 and provides the same interrupts, serial interface and timer, executing most of instructions in a single clock cycle.

The C32025TX is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with both-edge clocking, a synchronous reset, and no internal tri-states.

See representative implementation results (each in a new pop-up window):

ASIC numbers Altera numbers Lattice numbers Xilinx numbers

Applications

The C32025TX core is suitable for implementing a wide range of digital signal processing applications such as:

Block Diagram

c32025tx block diagram

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements. It has also been successfully implemented in commercial and prototype systems..

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

 

 

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