The following are typical performance and utilization results using Xilinx devices. Core configured with 4096x16 ROM and 256x16 + 256x16 + 32x16 RAM. Slices are optimized for speed and IOBs results assume all I/O are routed off-chip.
| Xilinx Devices | Slices |
BRAM | DSP48 | IOBs | System Clock |
ISE Version |
| Spartan-3E XC3S1200E-5 |
2347 | 2 | - | 59 | 45 MHz | 12.1i |
| Spartan-6 XC6SLX150T-3 |
904 | 3 | 1 | 59 | 70 MHz | 12.1i |
| Virtex-5 XC5VLX110-3 |
995 | 2 | 1 | 59 | 110 MHz | 12.1i |
| Virtex-6 XC6VLX240T-3 |
879 | 4 | 1 | 59 | 125 MHz | 12.1i |