- Control Unit
- 16-bit instruction decoding
- Repeat instructions for efficient use of program space and enhanced execution
- Central Arithmetic-Logic Unit
- 16-bit parallel shifter; 32-bit arithmetic and logical operations
- 16 x 16 bit parallel multiplier with a 32-bit product
- 32-bit accumulator with output shifter
- Single-cycle Multiply-and-Accumulate instructions
- Auxiliary Registers
- 8 16-bit registers for indirect addressing or temporary data storage
- 16-bit Auxiliary Register Arithmetic Unit including operations with reversed-carry propagation
- Memory addressing modes
- Direct - using a 9-bit Page Pointer and instruction word’s lowest 7-bits
- Indirect – using the Auxiliary Register File
- Immediate – less than 16-bit via instruction word or full 16-bit long immediate following the instruction word
- Block moves for data/program management
- 8-level Hardware Stack
- Interrupt Controller: 6 interrupt sources, excluding reset and a software interrupt
- Synchronous serial port for direct codec interface
- 16-bit reload timer
- Program Memory organization
- 4K-words of internal ROM
- Internal 256-word RAM block configurable either as program or data space
- 64K-word external program space
- Data Memory organization
- 2 Internal 256-word and one 32-word RAM blocks
- 64K-words of external data space
- 6 memory mapped registers
- 16 Input and 16 Output channels
- Wait states for interfacing slower off-chip devices
- Multiprocessing support
- Global data memory interface
- Synchronization input for synchronous multiprocessor configurations
- Concurrent DMA using an extended Hold operation
- Design is strictly synchronous with positive-edge clocking and synchronous reset, no internal tri-states.
Call or click.
- C32025TX 16-bit Fixed-Point Digital Signal Processor
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Electronic News - Design Entry, IP Highlight DATE
32025 DSP IP Core C32025 16-bit Digital Signal Processor (DSP) Core
The C32025 is a 16-bit fixed-point digital signal processor core. It combines the flexibility of a high-speed controller with the numerical capability of an array processor. The C32025 has the same instruction set as the TMS320C25 and also provides the same interrupts, serial interface and timer.
The architecture of the C32025 ensures overall system speed and flexibility in processor configuration. The instruction set and control signals provide block memory transfers, communication to slower off-chip devices and multiprocessing implementations. Single-cycle multiply/accumulate instructions, two large on-chip RAM blocks, eight auxiliary registers with a dedicated arithmetic unit, serial interface and a hardware timer make the processor appropriate for data-intensive signal processing.
The C32025 implements Harvard-type architecture to maximize processing power by maintaining two separate program and data buses for full-speed execution. The program bus carries the instructions and immediate operands while the data bus interconnects various components and carries data from/to any data memory space. Both buses can carry data for multiply/accumulate single-cycle operations.
Instruction flow consists of three pipeline stages, essentially invisible to the user. The pre-fetch, decode and execute operations are independent, that allows instruction executions to overlap. Thus, three different instructions can be active during any given cycle.
Most instructions can be used in repeat mode, when executed a given number of times. This feature is most useful with block moves, multiply/accumulates, I/O transfers and table read/writes.
Developed for easy reuse with ASICs or FPGAs, the core requires under 18000 ASIC gates.
The C32025 can be utilized for a variety of signal processing applications including:
- Digital sound processing (adaptive filtering, FFT, other special sound effects)
- Voice recognition
- Telecommunications (modems, codecs)
- Medical equipment (diagnostics tools)
- Computers peripherals
- Various embedded data-intensive systems
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The C32025 core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model that contained the original Texas Instruments TMS320C25 chip, and the results compared with the core’s simulation outputs.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Example CHIP_C32025 – TMS320C25 compatible design. This design uses the C32025 and illustrates how to build and connect memories and tri-state buffers
- Sophisticated HDL Testbench including vectors that instantiates:
- Example design CHIP_C32025
- External RAM
- External ROM
- External I/O
- Clock generator
- Process that compares your simulation results with the expected results
- A collection of test assembler programs which are executed directly by the Test Bench
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including architectural overview, hardware description, user guide, design support including consultation