Memory IP Core DMA32 Direct Memory Access Controller IP Core

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Support | Verification | Deliverables | Related Platforms and Cores

This DMA IP core implements a configurable, single-channel, direct memory access controller for the 32-bit wide AHB bus. It conforms to the Advanced Micro controller Bus Architecture 2.0 (AMBA) specification.

The DMA32 controller contains useful features such as incrementing and non-incrementing addressing, linked list operation, and interrupt control to alert the processor to the DMA’s status.

Non-incrementing addressing is useful for transferring data to and from peripherals with FIFOs or a single data port.  Incrementing addressing is useful for transferring data to and from memories or peripherals containing memory. Linked list support is useful for non-contiguous memory transfer operations.

The DMA32 controller acts as a bus master device that controls data block transfers from a source memory or peripheral to a destination memory or peripheral.  The controller can implement multiple DMA channels simply by instantiating more than one controller on the AMBA AHB bus. Arbitration is handled by the AHB system bus.

See representative implementation results (each in a new pop-up window):

Features

• AHB Master/Slave DMA Controller
• Single Channel, multiple instantiation
• Modes
• Memory to Memory
• Memory to Peripheral
• Peripheral to Memory
• Peripheral to Peripheral
• Source and destination address descriptors
• Single word and burst transfer requests
• Programmable burst size
• Current address status
• Incrementing, wrapping, and non incrementing addressing
• Linked list support
• Transfer complete interrupt
• Low gate count, e.g., under 11,000 gates for 90nm ASIC
• Scatter-gather support allows DMA to merge multiple data sources into contiguous space
• Supports both hardware initiated transfers and software initiated transfers
• Supports 8-, 16-, or 32-bit wide transfers
• Supports burst transfer to maximize data bandwidth
• Bus Interface designed for high-speed access to any AHB slave device
• Handles wait-state insertion by any AHB slave device
• Supports all responses from an AHB slave device: OK, SPLIT, RETRY, ERROR

Applications

The DMA32 controller is suitable for a variety of applications requiring data transfers without the use of a processor such as:

• Microprocessor subsystems (specifically AMBA 2.0 AHB systems)
  
• Display systems
• USB, Ethernet, and Serial Communications
• Encryption/Decryption systems
• Data processing

Block Diagram

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available; contact CAST Sales.

Verification

The core has been verified through extensive simulation and system level prototyping using ARM based systems.  It has also been successfully embedded in several products.   

Deliverables

The core is available in ASIC (synthesizable Verilog) or FPGA (netlist) forms, and includes everything required for successful implementation:

• AMBA Bus Functional Model (Verilog)
• Sophisticated self-checking Testbench (Verilog)
• Simulation script, vectors, expected results, and comparison utility;
• Synthesis script or place and route script
• Comprehensive user documentation, including detailed specifications, software guide,  and a system integration guide

Related Platforms and Cores

Platforms

• PiP-AMBA Platform

Cores

• AHB Channel
• APB Channel
• AMBA AHB to APB bridge
• AHB Arbiter
• AHB External Bus Interface
• AHB Internal Synchronous SRAM Controller
• AHB Interrupt Controller
• AHB TFT LCD Controller
• AHB STN LCD Controller
• APB General Purpose IO
• APB Parallel-Printer Port
• APB Pulse Width Modulator
• APB Real Time Clock
• APB Counter-Timer
• APB 16450/16550 Compatible UART
• APB Watchdog Timer

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Support | Verification | Deliverables | Related Platforms and Cores

Download PDF datasheets for more info: ASIC | Altera | Xilinx