- Enable/Disable control of individual DMA requests
- Four, independent DMA channels
- Independent auto-initialization of all channels
- Memory-to-Memory transfers
- Memory block initialization
- Address increment or decrement
- Directly expandable to any number of channels
- End of process input for terminating transfers
- Software DMA requests
- Independent polarity control for DREQ and DACK signals
- The C8237 was developed in HDL and synthesizes to approximately 5,500 gates depending on the technology used
- Functionality based on the Intel 8237
C8237 Programmable DMA Controller Core
The C8237 Programmable DMA Controller core (C8237 core) is a peripheral interface circuit for microprocessor systems. The core is designed for use with an external, 8-bit address latch. It contains four independent channels and may be expanded to any number or channels by cascading additional controller chips. Each channel has a full 64K address and word count capability.
This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements. Meanwhile, we provide the following representative results (each in a new pop-up window):
The C8237 core is designed to improve system performance by allowing external devices to directly transfer information from the system memory.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core has been verified through extensive simulation and rigorous code coverage measurements.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Wrapper for matching the I/O of the original device
- Sophisticated HDL Testbench
- Simulation script, vectors, and expected results
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide