CAST Multi-Core Reference Design Demo System

Visit CAST at various industry events, and see our H.264 and other cores running in a reference design we developed.

The system's main board us a V-5 TAI Logic Module, one of the prototyping solutions offered by our partner S2C

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Several CAST IP cores are implemented in a Xilinx Virtex-5 device on the board:

• The CPXP-EP PCI Express Endpoint Controller core handles communication to and from a host PC or laptop system. It only needs a single lane (x1), but four (x4) and eight (x8) lane versions are available for applications requiring greater bandwidth.
• The H264-E is a new version of our H.264/AVS encoder core optimized to achieve high-quality video results with minunum silicon resources. In the demo, the H.264 core reads a video file in standard YUV format and accepts various compession parameters set through a GUI on the host system. It then produces H.264 video, which is sent through the PCIe connection for streamiing display or file storage.
• The DDR2-SDRAM-CTRL is a DDR/DDR2 SDRAM Memory Controller core that works with the H.264 encoder.
• The CMMI AHB is an unreleased CAST Multi-Media Interface core we developed to enable smoother integration between our H.264, JPEG2000, JPEG, and other cores with a system bus (AMBA AHB in this case).

If you can't make it to an event to see the demo in action, contact CAST sales any time by phone (+1 201=391-8300) or submit an information request to us for more details..