CAST IP Deliverables

We want you to be successful and have no problems with our products. So we strive to deliver a complete package of high-quality materials with every core. Deliverable details vary, but generally include:

• HDL RTL source code in Verilog or VHDL, or
  a post-synthesis EDIF netlist optimized for a specific FPGA or Structured ASIC device
• An example chip implementation, which uses the core in a sample system
• A sophisticated, self-checking HDL Testbench that includes everything needed to test the core (Verilog versions use Verilog 2001)
• Simulation script, vectors, and expected results
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications, a verification guide, and a system integration guide

Additional design aids are available for many cores (some are extra-cost options) including:

• Bit-accurate simulation models (BAMs)
• Configuration wizards
• Reference design boards

Check the Deliverables list on each product page for details, or contact CAST Sales for specifics on any of our products.