ZipAccel-D Core — XILINX FPGA Results

The ZipAccel-D can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). ZipAccel-D silicon resources requirements and throughput depends on its configuration. Also ZipAccel-D performance can scale by using multiple core instances. The following table provides sample performance and resource utilization data for different configurations of the core on an Kintex Ultrascale device, and do not represent the smallest possible area requirements nor the highest possible clock frequency.. Please contact CAST to get characterization data for your target configuration and technology.

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Device

Huffman
Tables

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Freq.
(MHz)

LUTs

BRAMs

Gbps

Kintex
UltraScale
xcku060-2

Dynamic

8,192

125

8,221

23.0

3.00

Dynamic

16,384

130

8,243

25.0

3.12

Dynamic

32,768

125

8,250

29.0

3.00

Static

8,192

165

5,375

4.5

3.96

Static

16,384

165

5,416

6.5

3.96

Static

32,768

165

5,392

10.5

3.96

 

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