ZipAccel-D Core — XILINX FPGA Results

ZipAccel-D silicon resources requirements and throughput depends on its configuration. Also ZipAccel-D performance can scale by using multiple core instances.

The following are sample implementation results for different configurations of the core on an Kintex Ultrascale device, and do not represent the smallest possible area requirements nor the highest possible clock frequency.

Family /
Device

Huffman
Tables

History
Window

Freq.
(MHz)

LUTs

BRAMs

Gbps

Kintex
UltraScale
xcku060-2

Dynamic

8,192

125

8,221

23.0

3.00

Dynamic

16,384

130

8,243

25.0

3.12

Dynamic

32,768

125

8,250

29.0

3.00

Static

8,192

165

5,375

4.5

3.96

Static

16,384

165

5,416

6.5

3.96

Static

32,768

165

5,392

10.5

3.96

Contact CAST Sales for help defining likely configuration options and estimating implementation results for your specific system.

close window