ZipAccel-D Core — Intel Implementation Results

The ZipAccel-D can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). ZipAccel-D silicon resources requirements and throughput depends on its configuration. Also ZipAccel-D performance can scale by instantiating more Huffman decoders and by using multiple core instances. The following table provides sample performance and resource utilization data for different configurations of the core on an Arria10 device, and do not represent the smallest possible area requirements nor the highest possible clock frequency. Please contact CAST to get characterization data for your target configuration and technology.

Family /
Device

Huffman
Tables

History
Window

Freq.
(MHz)

ALMs

Memory
Bits

Gbps

Arria10
GX-1150

Dynamic

512

135

7,348

154,178

3.24

Dynamic

1,024

135

7,470

158,786

3.24

Dynamic

2,048

135

7,334

171,074

3.24

Dynamic

4,096

135

7,329

187,714

3.24

Dynamic

8,192

135

7,378

220,738

3.24

Dynamic

16,384

135

7,360

286,530

3.24

Dynamic

32,768

130

7,385

417,858

3.12

Static

512

160

4,914

25,680

3.84

Static

1,024

160

5,012

30,288

3.84

Static

2,048

135

4,824

42,576

3.24

Static

4,096

160

4,862

59,216

3.84

Static

8,192

125

4,882

92,240

3.00

Static

16,384

140

4,917

158,032

3.36

Static

32,768

155

4,957

289,350

3,72

 

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