Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
40G UDPIP Stack
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN PHY Daughter Card
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
IEEE 802.1AS Hardware
   Protocol Stack

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

Compression Standards

  • ZLIB (RFC-1950)
  • Inflate/Deflate (RFC-1951)
  • GZIP/GUNZIP (RFC-1952)

Inflate/Deflate Features

  • Up to 32KB history window size
  • All deflate block types
    • Static and Dynamic Huffman-Coded blocks
    • Stored Deflate Blocks

High Performance & Low Latency

  • Three bytes per clock average processing rate, for throughputs exceeding 20Gbps with a single core, and scalable to more than 100Gbps with multiple core instances
  • Latency from 20 clock cycles for Static Huffman blocks, and typically less than 2000 cycles for Dynamic Huffman Blocks

Easy to Use and Integrate

  • Processor-free, standalone operation 
  • Extensive Error Catching & Reporting for Smooth Operation and Recovery in the presence of Errors
    • Header Syntax Errors
    • CRC/Adler 32 Errors
    • File Size Errors
    • Coding errors
    • Huffman Tables Errors
    • Non-correctable ECC memory errors
  • Optional ECC memories, necessary for Enterprise-Class RASM 
  • Streaming-capable, optionally bridged to AMBA AXI4-Stream interfaces
  • Microcode-free, scan-ready design

Configuration Options

  • Synthesis time configuration options allow fine tuning the core’s size and performance:
    • Input and output bus width
    • FIFO sizes
    • Maximum History Window
    • Static-Only or Dynamic and Static Huffman Tables support
    • Two or three decompressed bytes per cycle throughput

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

Options

  • Easily build boards using this core with PLDA's QuickPlay software-defined FPGA development platform

News Releases

Latest White Paper

  • Innovative Energy Savings Using GZIP IP Within IoT Devices 
(D&R IP-SoC 2015 Paper)

    Innovative Energy Savings Using GZIP IP Within IoT Devices (D&R IP-SoC 2015 Paper)

    In this paper we look at how IP cores for hardware GZIP/Deflate based data compression and decompression can significantly reduce power consumption in large categories of IoT devices. We will further show through multiple examples that the power reductions to be gained far exceeds the active and idle power usage of the additional compression and decompression cores.

  • White Paper — Firmware Compression for Lower Energy and Faster Boot in IoT Devices

    White Paper — Firmware Compression for Lower Energy and Faster Boot in IoT Devices

    IoT devices that employ code shadowing can enjoy significant energy savings by using efficient hardware code compression. The compressed application code needs a smaller NVM device for long-term storage, and the system consumes significantly less time and energy reading the compressed code from the system's non-volatile memory (NVM) into the on-chip SRAM. The code can be decompressed in-line (as it is read out of the NVM), at the cost of practically negligible additional delay or energy usage.

See more White Paper blog posts >>>

Blog Posts

Applicable Standards

Background & More Info

ZipAccel-D GUNZIP/ZLIB/Inflate Data Decompression Core

ZipAccel-D is a custom hardware implementation of a lossless data decompression engine that complies with the Inflate/Deflate, GZIP/GUNZIP, and ZLIB compression standards.

GUNZIP/ZLIB/Inflate Data Decompression block diagram for the ZipAccel-D IP core from CAST

The core features fast processing, with low latency and high throughput. On average the core outputs three bytes of decompressed data per clock cycle, providing over 15Gbps in a typical 40nm technology. Designers can scale the throughput further by instantiating the core multiple times to achieve throughput rates exceeding 100Gbps.The latency is in the order of few tens of clock cycles for blocks coded with static Huffman tables, and typically less than 2,000 cycles for block encoded with dynamic Huffman tables.

Hardware GZIP compression IP with high throughouput, low latency, and a flexible, scalable designThe decompression core has been designed for ease of use and integration. It operates on a standalone basis, off-loading the host CPU from the demanding task of data decompression. The core receives compressed input files and outputs decompressed files. No preprocessing of the compressed files is required, as the core parses the file headers, checks the input files for errors, and outputs the decompressed data payload. Featuring extensive error tracking and reporting errors, the core enables smooth system operation and error recovery, even in the presence of errors in the compressed input files.  Furthermore, internal memories can optionally support Error Correction Codes (ECC) to simplify achievement of Enterprise Class reliability requirements.

The ZipAccel-D core is a microcode-free design developed for reuse in ASIC and FPGA implementations. Streaming data, optionally bridged to AMBA AXI4-stream, interfaces ease SoC integration. Technology mapping is straightforward, as the design is scan-ready, microcode-free, and uses easily replaceable, generic memory models. The core has been rigorously verified and production proven in a number of commercially available products.

See representative implementation results (each in a new pop-up window):

gzip decompression IP samples on Altera devices GZIP/Inflate decompression IP on Xilinx devices

Applications

The ZipAccel-D core is ideal for increasing the bandwidth of optical, wired or wireless data communication links, and for increasing the capacity of data storage in a wide range of devices such as networking interface/routing/storage equipment, data servers, or SSD drives. The core can also help reduce the power consumption and bandwidth of centralized memories (e.g. DDR) or interfaces (e.g. Ethernet, Wi-Fi) in a wide range of SoC designs.

Performance and Area

ZipAccel-D silicon resources requirements and throughput depends on its configuration. Also ZipAccel-D performance can scale by using multiple core instances.

Over 100 Gbps throughputs are feasible, and the silicon footprint can be less than 200KGates. Contact CAST Sales for help defining likely configuration options and estimating implementation results for your specific system.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive synthesis, place and route, and simulation runs. It has also been embedded in several commercially-shipping products, and is proven in both ASIC and FPGA technologies.

The core has been verified for interoperability with a number of software applications that use GZIP, ZLIB, or deflates compression.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

 

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