- ZLIB (RFC-1950)
- Inflate/Deflate (RFC-1951)
- GZIP/GUNZIP (RFC-1952)
- Up to 32KB history window size
- All deflate block types
- Static and Dynamic Huffman-Coded blocks
- Stored Deflate Blocks
High Performance & Low Latency
- Three bytes per clock average processing rate, for throughputs exceeding 20Gbps with a single core, and scalable to more than 100Gbps with multiple core instances
Latency from 20 clock cycles for Static Huffman blocks, and typically less than 2000 cycles for Dynamic Huffman Blocks
Easy to Use and Integrate
- Processor-free, standalone operation
- Extensive Error Catching & Reporting for Smooth Operation and Recovery in the presence of Errors
- Header Syntax Errors
- CRC/Adler 32 Errors
- File Size Errors
- Coding errors
- Huffman Tables Errors
- Non-correctable ECC memory errors
- Optional ECC memories, necessary for Enterprise-Class RASM
- Streaming-capable, optionally bridged to AMBA AXI4-Stream interfaces
- Microcode-free, scan-ready design
- Synthesis time configuration options allow fine tuning the core’s size and performance:
- Input and output bus width
- FIFO sizes
- Maximum History Window
- Static-Only or Dynamic and Static Huffman Tables support
- Two or three decompressed bytes per cycle throughput
Call or click.
- Reference Design: GZIP-RD-A10 PCIe GZIP Compression Acceleration Card Reference Design for Intel Boards
- Reference Design: GZIP-RD-XDMA PCIe GZIP Compression Acceleration Card Reference Design for Xilinx Boards
- Compressor: ZipAccel-C GZIP/ZLIB/Deflate Data Compression Core
- Easily build boards using this core with PLDA's QuickPlay software-defined FPGA development platform
Latest White Paper
In this paper we look at how IP cores for hardware GZIP/Deflate based data compression and decompression can significantly reduce power consumption in large categories of IoT devices. We will further show through multiple examples that the power reductions to be gained far exceeds the active and idle power usage of the additional compression and decompression cores.
IoT devices that employ code shadowing can enjoy significant energy savings by using efficient hardware code compression. The compressed application code needs a smaller NVM device for long-term storage, and the system consumes significantly less time and energy reading the compressed code from the system's non-volatile memory (NVM) into the on-chip SRAM. The code can be decompressed in-line (as it is read out of the NVM), at the cost of practically negligible additional delay or energy usage.
See more White Paper blog posts >>>
- Part 2 — John Blyler with Meredith Lucky at REUSE 2016
- Using GZIP Data Compression to Reduce Power Consumption in IoT Devices
- IoT Phase 2: Design Matters
- RFC 1952 – GZIP file format
- RFC 1950 – ZLIB Compressed Data Format
- RFC 1951 – DEFLATE Compressed Data Format
Background & More Info
ZipAccel-D GUNZIP/ZLIB/Inflate Data Decompression Core
ZipAccel-D is a custom hardware implementation of a lossless data decompression engine that complies with the Inflate/Deflate, GZIP/GUNZIP, and ZLIB compression standards.
The core features fast processing, with low latency and high throughput. On average the core outputs three bytes of decompressed data per clock cycle, providing over 15Gbps in a typical 40nm technology. Designers can scale the throughput further by instantiating the core multiple times to achieve throughput rates exceeding 100Gbps.The latency is in the order of few tens of clock cycles for blocks coded with static Huffman tables, and typically less than 2,000 cycles for block encoded with dynamic Huffman tables.
The decompression core has been designed for ease of use and integration. It operates on a standalone basis, off-loading the host CPU from the demanding task of data decompression. The core receives compressed input files and outputs decompressed files. No preprocessing of the compressed files is required, as the core parses the file headers, checks the input files for errors, and outputs the decompressed data payload. Featuring extensive error tracking and reporting errors, the core enables smooth system operation and error recovery, even in the presence of errors in the compressed input files. Furthermore, internal memories can optionally support Error Correction Codes (ECC) to simplify achievement of Enterprise Class reliability requirements.
The ZipAccel-D core is a microcode-free design developed for reuse in ASIC and FPGA implementations. Streaming data, optionally bridged to AMBA AXI4-stream, interfaces ease SoC integration. Technology mapping is straightforward, as the design is scan-ready, microcode-free, and uses easily replaceable, generic memory models. The core has been rigorously verified and production proven in a number of commercially available products.
This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements. Meanwhile, we provide the following representative results (each in a new pop-up window):
The ZipAccel-D core is ideal for increasing the bandwidth of optical, wired or wireless data communication links, and for increasing the capacity of data storage in a wide range of devices such as networking interface/routing/storage equipment, data servers, or SSD drives. The core can also help reduce the power consumption and bandwidth of centralized memories (e.g. DDR) or interfaces (e.g. Ethernet, Wi-Fi) in a wide range of SoC designs.
Performance and Area
ZipAccel-D silicon resources requirements and throughput depends on its configuration. Also ZipAccel-D performance can scale by using multiple core instances.
Over 100 Gbps throughputs are feasible, and the silicon footprint can be less than 200KGates. Contact CAST Sales for help defining likely configuration options and estimating implementation results for your specific system.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core has been verified through extensive synthesis, place and route, and simulation runs. It has also been embedded in several commercially-shipping products, and is proven in both ASIC and FPGA technologies.
The core has been verified for interoperability with a number of software applications that use GZIP, ZLIB, or deflates compression.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated Test Environment
- Simulation scripts, test vectors and expected results
- Synthesis script
- Comprehensive user documentation