ZipAccel-C Core — Intel Implementation Results

The ZipAccel-C can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The ZipAccel-C performance can scale by instantiating more search engines and/or Huffman decoders. Furthermore, other design options such as the search area window affect the silicon resources utilization. The following table provides sample Intel  results for a subset of the possible configuration options. They do not represent the smallest possible area requirements nor the highest possible clock frequency. Please contact CAST to get characterization data for your target configuration and technology.

Family Configuration ALMs RAM Bits
Stratix V
1 Search Engine, I Dynamic Huffman Encoder, 4KB History Window, 200MHz 10,768 781,294
Stratix V
4 Search Engines, I Dynamic Huffman Encoder, 4KB History Window, 200MHz 26,840 3,886,517
Stratix V
32 Search Engines, 4 Dynamic Huffman Encoders, 4KB History Window, 200MHz 240,969 32,370,088

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