Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
40G UDPIP Stack
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN PHY Daughter Card
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
IEEE 802.1AS Hardware
   Protocol Stack

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

Compression Standards

  • Deflate (RFC-1951)
  • ZLIB (RFC-1950)
  • GZIP (RFC-1952)

Deflate Features

  • LZ77 with configurable block and search window size
  • Static and Dynamic Huffman
  • Optional Stored Deflate Blocks
  • Dynamic Mode Selection

Flexible Architecture

  • Fine-tune Throughput, Compression Efficiency, and Latency to match application requirements
    • More than 100Gbps with one core instance, scalable to meet any throughput requirement
    • Compression efficiency can be on par with Unix/Linux max compression option (gzip -9)
    • Silicon requirements start from 20k gates
    • Under 15 clock cycles (Static Huffman)
  • Configuration Options
    • Search Engine and Huffman Encoder blocks Architecture
    • History Search Window Size (up to 32KB)
    • Deflate Block Size
    • Deflate Blocks Support
    • Parallel Processing Level

Easy to Use and Integrate

  • Processor-free, standalone operation
  • Streaming-capable interfaces and optional AMBA bus wrappers
  • Large file segmentation enables meeting QoS objectives
  • Microcode-free, scan-ready design
  • Optional ECC memories, necessary for Enterprise-Class RASM 
  • Optionally integrated with AES-XTS and AES-GCM encryption companion cores

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

Options

  • Easily build boards using this core with PLDA's QuickPlay software-defined FPGA development platform

News Releases

Latest White Paper

  • Innovative Energy Savings Using GZIP IP Within IoT Devices 
(D&R IP-SoC 2015 Paper)

    Innovative Energy Savings Using GZIP IP Within IoT Devices (D&R IP-SoC 2015 Paper)

    In this paper we look at how IP cores for hardware GZIP/Deflate based data compression and decompression can significantly reduce power consumption in large categories of IoT devices. We will further show through multiple examples that the power reductions to be gained far exceeds the active and idle power usage of the additional compression and decompression cores.

  • White Paper — Firmware Compression for Lower Energy and Faster Boot in IoT Devices

    White Paper — Firmware Compression for Lower Energy and Faster Boot in IoT Devices

    IoT devices that employ code shadowing can enjoy significant energy savings by using efficient hardware code compression. The compressed application code needs a smaller NVM device for long-term storage, and the system consumes significantly less time and energy reading the compressed code from the system's non-volatile memory (NVM) into the on-chip SRAM. The code can be decompressed in-line (as it is read out of the NVM), at the cost of practically negligible additional delay or energy usage.

See more White Paper blog posts >>>

Blog Posts

Applicable Standards

Background & More Info

ZipAccel-C GZIP/ZLIB/Deflate Data Compression Core

ZipAccel-C is a custom hardware implementation of a lossless data compression engine that complies with the Deflate, GZIP, and ZLIB compression standards.

GZIP/ZLIB/Deflate Data Compression Core ZipAccel-C block diagram from CAST

The core receives uncompressed input files and produces compressed files. No post processing of the compressed files is required, as the core encapsulates the compressed data payload with the proper headers and footers. Input files can be segmented, and segments from different files can be interleaved at the core’s input. 

The core’s flexible architecture enables fine-tuning of its compression efficiency, throughput, and latency to match the requirements of the end application. Throughputs in excess of 100 Gbps are feasible even in low-cost FPGAs, and latency can be as small as a few tens of clock cycles.

ZipAccel-C offers compression efficiency practically equivalent to today’s popular deflate-based software applications. Analyzing processing speed versus compression efficiency to achieve the best trade off for a specific system is facilitated by the included software model, and by support from our team of data compression experts.

Hardware GZIP compression IP with high throughouput, low latency, and a flexible, scalable designZipAccel-C has been designed for ease of use and integration. It operates on a standalone basis, off-loading the host CPU from the demanding task of data compression, and optionally from the task of encrypting the compressed stream. Streaming data interfaces and optional AMBA bus interfaces ease SoC integration.

Technology mapping is straightforward, as the design is scan-ready, microcode-free, and uses easily replaceable, generic memory models. Memory blocks can optionally support Error Correction Codes (ECC) to simplify achievement of Enterprise Class reliability requirements. Furthermore, input file segmentation can limit the inter-file latency and helps users achieve Quality of Service (QoS) objectives. The core has been rigorously verified and production proven in numerous commercial products.

GZIP compression IP core running on KU105 PCIe board reference design for easy evaluation or system developmentA PCIe GZIP reference design system is available for evaluating or building a system around this GZIP compression core.

See representative implementation results (each in a new pop-up window):

sample silicon results for GZIP compression IP on Altera devices hardware gzip compression sample results for Xilinx FPGAs

Applications

The ZipAccel-C core is ideal for increasing the bandwidth of optical, wired or wireless data communication links, and for increasing the capacity of data storage in a wide range of devices such as networking interface/routing/storage equipment, data servers, or SSD drives. The core can also help reduce the power consumption and bandwidth of centralized memories (e.g. DDR) or interfaces (e.g. Ethernet, Wi-Fi) in a wide range of SoC designs.

Area and Performance

ZipAccel-C reference designs have been evaluated in a variety of technologies. ZipAccel-C performance can scale by instantiating more search engines and/or Huffman decoders. Furthermore, other design options such as the search area window affect the silicon resources utilization.

Over 100 Gbps throughputs are feasible, and the silicon footprint can be less than 100KGates. Contact CAST Sales for help defining likely configuration options and estimating implementation results for your specific system.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive synthesis, place and route, and simulation runs. It has also been embedded in several commercially-shipping products, and is proven in both ASIC and FPGA technologies.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

 

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