- Deflate (RFC-1951)
- ZLIB (RFC-1950)
- GZIP (RFC-1952)
- LZ77 with configurable block and search window size
- Static and Dynamic Huffman
- Optional Stored Deflate Blocks
- Dynamic Mode Selection
- Fine-tune Throughput, Compression Efficiency, and Latency to match application requirements
- More than 100Gbps with one core instance, scalable to meet any throughput requirement
- Compression efficiency can be on par with Unix/Linux max compression option (gzip -9)
- Silicon requirements start from 20k gates
- Under 15 clock cycles (Static Huffman)
- Configuration Options
- Search Engine and Huffman Encoder blocks Architecture
- History Search Window Size (up to 32KB)
- Deflate Block Size
- Deflate Blocks Support
- Parallel Processing Level
Easy to Use and Integrate
- Processor-free, standalone operation
- Streaming-capable interfaces and optional AMBA bus wrappers
- Large file segmentation enables meeting QoS objectives
- Microcode-free, scan-ready design
- Optional ECC memories, necessary for Enterprise-Class RASM
- Optionally integrated with AES-XTS and AES-GCM encryption companion cores
Call or click.
- Reference Design: GZIP-RD-KU105 ZipAccel-C GZIP Compression PCIe Board Reference Design
- Decompressor: ZipAccel-D GUNZIP/ZLIB/Inflate Data Decompression Core
- Easily build boards using this core with PLDA's QuickPlay software-defined FPGA development platform
- 08/09/16, CAST and PLDA GROUP demonstrate x86-compliant high compression ratio GZIP acceleration on FPGA, accessible to non-FPGA experts using the QuickPlay Software Defined FPGA development tool
- 06/07/16, CAST Licenses GZIP Core to Tier 1 Wireless Chipset Vendor
Latest White Paper
In this paper we look at how IP cores for hardware GZIP/Deflate based data compression and decompression can significantly reduce power consumption in large categories of IoT devices. We will further show through multiple examples that the power reductions to be gained far exceeds the active and idle power usage of the additional compression and decompression cores.
IoT devices that employ code shadowing can enjoy significant energy savings by using efficient hardware code compression. The compressed application code needs a smaller NVM device for long-term storage, and the system consumes significantly less time and energy reading the compressed code from the system's non-volatile memory (NVM) into the on-chip SRAM. The code can be decompressed in-line (as it is read out of the NVM), at the cost of practically negligible additional delay or energy usage.
See more White Paper blog posts >>>
- Part 2 — John Blyler with Meredith Lucky at REUSE 2016
- Using GZIP Data Compression to Reduce Power Consumption in IoT Devices
- IoT Phase 2: Design Matters
- RFC 1952 – GZIP file format
- RFC 1950 – ZLIB Compressed Data Format
- RFC 1951 – DEFLATE Compressed Data Format
Background & More Info
ZipAccel-C GZIP/ZLIB/Deflate Data Compression Core
ZipAccel-C is a custom hardware implementation of a lossless data compression engine that complies with the Deflate, GZIP, and ZLIB compression standards.
The core receives uncompressed input files and produces compressed files. No post processing of the compressed files is required, as the core encapsulates the compressed data payload with the proper headers and footers. Input files can be segmented, and segments from different files can be interleaved at the core’s input.
The core’s flexible architecture enables fine-tuning of its compression efficiency, throughput, and latency to match the requirements of the end application. Throughputs in excess of 100 Gbps are feasible even in low-cost FPGAs, and latency can be as small as a few tens of clock cycles.
ZipAccel-C offers compression efficiency practically equivalent to today’s popular deflate-based software applications. Analyzing processing speed versus compression efficiency to achieve the best trade off for a specific system is facilitated by the included software model, and by support from our team of data compression experts.
ZipAccel-C has been designed for ease of use and integration. It operates on a standalone basis, off-loading the host CPU from the demanding task of data compression, and optionally from the task of encrypting the compressed stream. Streaming data interfaces and optional AMBA bus interfaces ease SoC integration.
Technology mapping is straightforward, as the design is scan-ready, microcode-free, and uses easily replaceable, generic memory models. Memory blocks can optionally support Error Correction Codes (ECC) to simplify achievement of Enterprise Class reliability requirements. Furthermore, input file segmentation can limit the inter-file latency and helps users achieve Quality of Service (QoS) objectives. The core has been rigorously verified and production proven in numerous commercial products.
A PCIe GZIP reference design system is available for evaluating or building a system around this GZIP compression core.
See representative implementation results (each in a new pop-up window):
The ZipAccel-C core is ideal for increasing the bandwidth of optical, wired or wireless data communication links, and for increasing the capacity of data storage in a wide range of devices such as networking interface/routing/storage equipment, data servers, or SSD drives. The core can also help reduce the power consumption and bandwidth of centralized memories (e.g. DDR) or interfaces (e.g. Ethernet, Wi-Fi) in a wide range of SoC designs.
Area and Performance
ZipAccel-C reference designs have been evaluated in a variety of technologies. ZipAccel-C performance can scale by instantiating more search engines and/or Huffman decoders. Furthermore, other design options such as the search area window affect the silicon resources utilization.
Over 100 Gbps throughputs are feasible, and the silicon footprint can be less than 100KGates. Contact CAST Sales for help defining likely configuration options and estimating implementation results for your specific system.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core has been verified through extensive synthesis, place and route, and simulation runs. It has also been embedded in several commercially-shipping products, and is proven in both ASIC and FPGA technologies.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated Test Environment
- Simulation scripts, test vectors and expected results
- Synthesis script
- Comprehensive user documentation