Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Serial NOR/NAND Flash
Octal, XIP, DMA for AHB
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
40G UDPIP Stack
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

MIPI
SPMI Master/Slave

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

Reference design of a GZIP & GUNZIP acceleration card using Xilinx FPGAs

Throughput

  • Scalable and only limited by silicon resources and/or PCIe throughput
  • Over 80 Gbps uncompressed data rate on VU9P with PCIe Gen3x16

Compression Efficiency

  • Configurable and up to software gzip level - 6

Hardware

  • Xilinx Kintex UltraScale FPGA KCU105 Evaluation Kit
  • Alpha Data ADM-PCIE-KU3 HPC Board
  • Xilinx Virtex UltraScale+ FPGA VCU1525 Acceleration Development Kit
  • Design portable to other boards and FPGA families

Software

  • Drivers for Linux Fedora-26 (portable to other Operating Systems on request)
  • Sample Application

Third-Party IP Cores

  • Xilinx IP
    • PCIe End Point controller
    • DMA for PCIe subsystem

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

News Releases

Applicable Standards

Background & More Info

GZIP-RD-XDMA GZIP & GUNZIP Accelerator Reference Design for Xilinx FPGAs

The GZIP-RD-XDMA is a reference design for a PCIe data compression and decompression acceleration card using the ZipAccel-C and ZippAccel-D GZIP/ZLIB/Deflate Compression and Decompression IP Cores.

The accelerator is highly efficient and can compress data at rates exceeding 80 Gbps, making it suitable for servers or databases where it optimizes storage requirements or network bandwidth.

The reference design uses Xilinx® DMA for PCIe subsystem (XDMA) and can be mapped on PCIe boards hosting 7-series, UltraScale™ or  UltraScale+™ devices.  The following table summarizes available off-the-shelf compression-only configurations for Xilinx FPGA boards:

GZIP-DMA-Demos-Table

gzip-rd-xdma-Xilinx-Block-Diagram

The accelerator’s compression engines, the ZipAccel-C and ZipAccel-D IP cores, are highly configurable and can be tuned to meet different application requirements with respect to silicon resources utilization, compression efficiency, and throughput. CAST will work with you to define the cores’ configuration that meets your application requirements.

The reference design is delivered with a sample GUI-driven application, which designers can use to evaluate the performance of the ZipAccel-C and ZipAccel-D cores or as a basis to develop their own application.

Deliverables include the firmware (FPGA programming file), software (drivers & sample application), and comprehensive documentation, but please note that the FPGA board has to be purchased separately.

For more information please contact CAST sales.

 

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