- Scalable and only limited by silicon resources and/or PCIe throughput
- Over 80 Gbps uncompressed data rate on VU9P with PCIe Gen3x16
- Configurable and up to software gzip level - 6
- Xilinx Kintex UltraScale FPGA KCU105 Evaluation Kit
- Alpha Data ADM-PCIE-KU3 HPC Board
- Xilinx Virtex UltraScale+ FPGA VCU1525 Acceleration Development Kit
- Design portable to other boards and FPGA families
- Drivers for Linux Fedora-26 (portable to other Operating Systems on request)
- Sample Application
Third-Party IP Cores
- Xilinx IP
- PCIe End Point controller
- DMA for PCIe subsystem
Call or click.
- Compressor: ZipAccel-C GZIP/ZLIB/Deflate Data Compression Core
- Decompressor: ZipAccel-D GUNZIP/ZLIB/Inflate Data Decompression Core
- 10/17/17, CAST Introduces GZIP Accelerator Through New Intel FPGA Data Center Acceleration Ecosystem
- 05/16/17, Novatek Reduces TV Boot Time with Data Decompression IP Core from CAST
- 08/09/16, CAST and PLDA GROUP demonstrate x86-compliant high compression ratio GZIP acceleration on FPGA, accessible to non-FPGA experts using the QuickPlay Software Defined FPGA development tool
- RFC 1952 – GZIP file format
- RFC 1950 – ZLIB Compressed Data Format
- RFC 1951 – DEFLATE Compressed Data Format
Background & More Info
GZIP-RD-XDMA GZIP & GUNZIP Accelerator Reference Design for Xilinx FPGAs
The GZIP-RD-XDMA is a reference design for a PCIe data compression and decompression acceleration card using the ZipAccel-C and ZippAccel-D GZIP/ZLIB/Deflate Compression and Decompression IP Cores.
The accelerator is highly efficient and can compress data at rates exceeding 80 Gbps, making it suitable for servers or databases where it optimizes storage requirements or network bandwidth.
The reference design uses Xilinx® DMA for PCIe subsystem (XDMA) and can be mapped on PCIe boards hosting 7-series, UltraScale™ or UltraScale+™ devices. The following table summarizes available off-the-shelf compression-only configurations for Xilinx FPGA boards:
The accelerator’s compression engines, the ZipAccel-C and ZipAccel-D IP cores, are highly configurable and can be tuned to meet different application requirements with respect to silicon resources utilization, compression efficiency, and throughput. CAST will work with you to define the cores’ configuration that meets your application requirements.
The reference design is delivered with a sample GUI-driven application, which designers can use to evaluate the performance of the ZipAccel-C and ZipAccel-D cores or as a basis to develop their own application.
Deliverables include the firmware (FPGA programming file), software (drivers & sample application), and comprehensive documentation, but please note that the FPGA board has to be purchased separately.
For more information please contact CAST sales.