- PCIe board reference design for ZipAccel-C Core evaluation or application development.
- 23 Gbps (or higher upon request) uncompressed data rate
- Fully Compliant to GZIP (RFC-1952)
- Xilinx® Kintex® UltraScale™ FPGA KCU105 Evaluation Kit
- Design portable to other boards and FPGA families
- Drivers for Linux Fedora-20 or later (portable to other Operating Systems on request)
- Sample Application
Third-Party IP Cores
- Xilinx IP
- PCIe End Point controller
- AXI Interconnect
- NorthWest Logic IP
- AXI-to-PCIe Bridge
- Expresso DMA Core
Call or click.
- Compressor: ZipAccel-C GZIP/ZLIB/Deflate Data Compression Core
- Decompressor: ZipAccel-D GUNZIP/ZLIB/Inflate Data Decompression Core
- 05/16/17, Novatek Reduces TV Boot Time with Data Decompression IP Core from CAST
- 08/09/16, CAST and PLDA GROUP demonstrate x86-compliant high compression ratio GZIP acceleration on FPGA, accessible to non-FPGA experts using the QuickPlay Software Defined FPGA development tool
- 06/07/16, CAST Licenses GZIP Core to Tier 1 Wireless Chipset Vendor
Latest White Paper
IoT devices that employ code shadowing can enjoy significant energy savings by using efficient hardware code compression. The compressed application code needs a smaller NVM device for long-term storage, and the system consumes significantly less time and energy reading the compressed code from the system's non-volatile memory (NVM) into the on-chip SRAM. The code can be decompressed in-line (as it is read out of the NVM), at the cost of practically negligible additional delay or energy usage.
See more White Paper blog posts >>>
- Part 2 — John Blyler with Meredith Lucky at REUSE 2016
- Using GZIP Data Compression to Reduce Power Consumption in IoT Devices
- IoT Phase 2: Design Matters
- RFC 1952 – GZIP file format
- RFC 1950 – ZLIB Compressed Data Format
- RFC 1951 – DEFLATE Compressed Data Format
Background & More Info
GZIP-RD-KU105 ZipAccel-C GZIP PCIe Reference Design
The GZIP-RD-KU105 is a reference design for a PCIe data compression acceleration card using the ZipAccel-C GZIP/ZLIB/Deflate Compression IP Core.
The design runs on the Xilinx® Kintex® UltraScale™ FPGA KCU105 Evaluation Kit and it is built on top of Xilinx’s KCU105 PCI Express Streaming Data Plane targeted reference design (TRD). The package includes Linux Kernel drivers and a sample GUI-driven application.
The reference design achieves lossless data compression rates exceeding 23 Gbps. The reference design is suitable for servers or databases where it optimizes storage requirements or network bandwidth. Designers can use the sample application to evaluate the performance of the ZipAccel-C core, or can develop their own application using the API to the drivers.
The compression core itself can provide throughputs exceeding 60 Gbps. Modifications to the reference design to achieve higher rates or to port the design to other boards or FPGA devices are available.
Included GUI for control and monitoring of the reference design.