Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

  • PCIe board reference design for ZipAccel-C Core evaluation or application development.
ip cores for gzip/deflate lossless data compression icon

GZIP Acceleration

  • 23 Gbps (or higher upon request) uncompressed data rate
  • Fully Compliant to GZIP (RFC-1952)

Hardware

  • Xilinx® Kintex® UltraScale™ FPGA KCU105 Evaluation Kit
  • Design portable to other boards and FPGA families

Software

  • Drivers for Linux Fedora-20 or later (portable to other Operating Systems on request)
  • Sample Application

Third-Party IP Cores

  • Xilinx IP
    • PCIe End Point controller
    • AXI Interconnect
  • NorthWest Logic IP
    • AXI-to-PCIe Bridge
    • Expresso DMA Core

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

News Releases

Latest White Paper

  • White Paper — Firmware Compression for Lower Energy and Faster Boot in IoT Devices

    White Paper — Firmware Compression for Lower Energy and Faster Boot in IoT Devices

    IoT devices that employ code shadowing can enjoy significant energy savings by using efficient hardware code compression. The compressed application code needs a smaller NVM device for long-term storage, and the system consumes significantly less time and energy reading the compressed code from the system's non-volatile memory (NVM) into the on-chip SRAM. The code can be decompressed in-line (as it is read out of the NVM), at the cost of practically negligible additional delay or energy usage.

See more White Paper blog posts >>>

Blog Posts

Applicable Standards

Background & More Info

GZIP-RD-KU105 ZipAccel-C GZIP PCIe Reference Design

The GZIP-RD-KU105 is a reference design for a PCIe data compression acceleration card using the ZipAccel-C GZIP/ZLIB/Deflate Compression IP Core.
 

GZIP/ZLIB/Deflate Data Compression Core ZipAccel-C block diagram from CAST

The design runs on the Xilinx® Kintex® UltraScale™ FPGA KCU105 Evaluation Kit and it is built on top of Xilinx’s KCU105 PCI Express Streaming Data Plane targeted reference design (TRD). The package includes Linux Kernel drivers and a sample GUI-driven application.

The reference design achieves lossless data compression rates exceeding 23 Gbps. The reference design is suitable for servers or databases where it optimizes storage requirements or network bandwidth. Designers can use the sample application to evaluate the performance of the ZipAccel-C core, or can develop their own application using the API to the drivers.

The compression core itself can provide throughputs exceeding 60 Gbps. Modifications to the reference design to achieve higher rates or to port the design to other boards or FPGA devices are available.

GUI for control and monitoring of the reference design

  
 
 
 
 
 
 
 
Included GUI for control and monitoring of the reference design.

 

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