PCIe board data compression reference design for evaluating or developing with ZipAccel Compression or Decompression Cores
GZIP Acceleration
- 40 Gbps (or higher upon request) uncompressed data rate
- High compression efficiency (comparable to software gzip-6)
- Fully Compliant to the GZIP standard (RFC-1952)
Supported Hardware
- Intel Programmable Acceleration Card (Intel PAC) with Intel Arria 10 GX FPGA
- Bitware A10PL4 (Intel Arria 10)
- Reflex CES XpressGXA10-LP1150B (Intel Arria 10)
- Design portable to other boards and FPGA families
Software Interface
- Intel DCP Drivers
- Works with libraries and frameworks using Intel Xeon Acceleration Stack for Xeon CPU with FPFAs
Contact Sales
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Downloads (PDFs)
Related Products
- Compressor: ZipAccel-C GZIP/ZLIB/Deflate Data Compression Core
- Decompressor: ZipAccel-D GUNZIP/ZLIB/Inflate Data Decompression Core
- GZIP-RD-XIL GZIP & GUNZIP Accelerator Reference Design for Xilinx FPGAs
Intel® Programmable Acceleration Card (Intel PAC)
News Releases
Applicable Standards
- RFC 1952 – GZIP file format
- RFC 1950 – ZLIB Compressed Data Format
- RFC 1951 – DEFLATE Compressed Data Format
Background & More Info
Data Compression in Solid State Storage, presentation at Flash Memory Summit 2013 (PDF)- Wikipedia entries on GZIP, ZLIB, and Deflate
- An explanation of the Deflate algorithm by Antaeus Feldspar
GZIP Project website- ZLIB Project website
GZIP-RD-INT GZIP & GUNZIP Acceleration Card Reference Design for Intel’s PAC Board
The GZIP-RD-INT is a reference design for an FPGA PCIe data compression acceleration card. It uses the ZipAccel-C and ZippAccel-D GZIP/ZLIB/Deflate Compression and Decompression IP Cores.
The accelerator is highly efficient and can compress data at rates exceeding 40 Gbps, making it suitable for servers or databases where it optimizes storage requirements or network bandwidth.
The GZIP-RD-INT is available as a ‘drop-in’ accelerator function for the Intel® Programmable Acceleration Card (Intel PAC) with Intel Arria 10 GX FPGA. Some of the off-the-shelf configurations for this board are shown below:
The reference design is delivered with a sample GUI-driven application, which designers can use to evaluate the performance of the ZipAccel-C and ZipAccel-D cores or as a basis to develop their own application. Intel’s DCP drivers facilitate integration with application software. The reference design pulls in frameworks and libraries using the Intel Acceleration Stack for Intel Xeon CPU with FPGAs, easing the use of FPGA acceleration in Xeon-based systems.
The ZipAccel-C and Zipaccel-D IP cores are highly configurable and can be tuned to meet different application requirements with respect to compression efficiency for specific data-types, latency and throughput. CAST will work with you to define the IP cores’ configuration that meets your application requirements.
Deliverables include the firmware (FPGA programming file), software (drivers), and comprehensive documentation, but please note that the FPGA board has to be purchased separately.
