Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Secure Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
Automotive Ethernet
TSN Endpoint Controller
CAN-to-TSN Gateway
LIN
LIN Bus Master/Slave
LIN Bus VIP
SENT/SAE J2716
Tx/Rx Controller

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

PCIe board data compression reference design for evaluating or developing with ZipAccel Compression or Decompression Cores

GZIP Acceleration

  • 40 Gbps (or higher upon request) uncompressed data rate
  • High compression efficiency (comparable to software gzip-6)
  • Fully Compliant to the GZIP  standard (RFC-1952)

Supported Hardware

  • Intel Programmable Acceleration Card (Intel PAC) with Intel Arria 10 GX FPGA
  • Bitware A10PL4 (Intel Arria 10)
  • Reflex CES XpressGXA10-LP1150B (Intel Arria 10)
  • Design portable to other boards and FPGA families

Software Interface

  • Intel DCP Drivers
  • Works with libraries and frameworks using Intel Xeon Acceleration Stack for Xeon CPU with FPFAs

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

Intel® Programmable Acceleration Card (Intel PAC)

News Releases

Applicable Standards

Background & More Info

GZIP-RD-INT GZIP & GUNZIP Acceleration Card Reference Design for Intel’s PAC Board

The GZIP-RD-INT is a reference design for an FPGA PCIe data compression acceleration card. It uses the ZipAccel-C and ZippAccel-D GZIP/ZLIB/Deflate Compression and Decompression IP Cores.

The accelerator is highly efficient and can compress data at rates exceeding 40 Gbps, making it suitable for servers or databases where it optimizes storage requirements or network bandwidth.

The GZIP-RD-INT is available as a ‘drop-in’ accelerator function for the Intel® Programmable Acceleration Card (Intel PAC) with Intel Arria 10 GX FPGA. Some of the off-the-shelf configurations for this board are shown below:

 

The reference design is delivered with a sample GUI-driven application, which designers can use to evaluate the performance of the ZipAccel-C and ZipAccel-D cores or as a basis to develop their own application. Intel’s DCP drivers facilitate integration with application software. The reference design pulls in frameworks and libraries using the Intel Acceleration Stack for Intel Xeon CPU with FPGAs, easing the use of FPGA acceleration in Xeon-based systems.

Block diagram for the GZIP Reference Design

The ZipAccel-C and Zipaccel-D IP cores are highly configurable and can be tuned to meet different application requirements with respect to compression efficiency for specific data-types, latency and throughput. CAST will work with you to define the IP cores’ configuration that meets your application requirements.

Deliverables include the firmware (FPGA programming file), software (drivers), and comprehensive documentation, but please note that the FPGA board has to be purchased separately.

 

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