- PCIe board data compression reference design for ZipAccel-C Core evaluation or application development.
- 40 Gbps (or higher upon request) uncompressed data rate
- High compression efficiency (comparable to software gzip-6)
- Fully Compliant to the GZIP standard (RFC-1952)
- Intel Programmable Acceleration Card (Intel PAC) with Intel Arria 10 GX FPGA
- Bitware A10PL4 (Intel Arria 10)
- Reflex CES XpressGXA10-LP1150B (Intel Arria 10)
- Cloud FPGA instances via Accelize’s QuickStore
- Design portable to other boards and FPGA families
- Intel DCP Drivers
- QuickPlay API
- Works with libraries and frameworks using Intel Xeon Acceleration Stack for Xeon CPU with FPFAs
Call or click.
Info on Intel Xeon with FPGA:
- Intel Xeon with FPGA Platform Overview
- Intel Acceleration Stack for Intel Xeon CPUs with FPGAs
- Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA
CAST IP Cores:
- Compressor: ZipAccel-C GZIP/ZLIB/Deflate Data Compression Core
- Decompressor: ZipAccel-D GUNZIP/ZLIB/Inflate Data Decompression Core
- 10/17/17, CAST Introduces GZIP Accelerator Through New Intel FPGA Data Center Acceleration Ecosystem
GZIP-RD-A10 PCIe GZIP Compression Acceleration Card Reference Design
The GZIP-RD-A10 is a reference design for an FPGA PCIe data compression acceleration card. It uses the ZipAccel-C GZIP/ZLIB/Deflate Compression IP Core, and has been designed with QuickPlay® in partnership with Accelize®.
The GZIP accelerator is highly efficient and can compress data at rates exceeding 40 Gbps, making it suitable for servers or databases where it optimizes storage requirements or network bandwidth.
The GZIP-RD-A10 is available as a ‘drop-in’ accelerator function for the Intel® Programmable Acceleration Card (Intel PAC) with Intel Arria 10 GX FPGA, as well as for Bitware’s A10PL4 and Reflex’s XpressGXA10-LP1150B FPGA boards. Different PCIe FPGA boards hosting an Arria10 FPGA device can be supported upon request.
The reference design is delivered with a sample GUI-driven application, which designers can use to evaluate the performance of the ZipAccel-C core or as a basis to develop their own application. Intel’s DCP drivers and the easy-to-use QuickPlay API facilitate integration with application software. The reference design pulls in frameworks and libraries using the Intel Acceleration Stack for Intel Xeon CPU with FPGAs, easing the use of FPGA acceleration in Xeon-based systems.
The accelerator’s compression engine, the ZipAccel-C IP core, is highly configurable and can be tuned to meet different application requirements with respect to compression efficiency for specific data-types, latency and throughput. CAST will work with you to define the ZipAccel-C configuration that meets your application requirements. The reference design using a typical ZipAccel-C configuration can be evaluated at https://www.fpga-as-a-service.com/.Deliverables include the firmware (FPGA programming file), software (drivers), and comprehensive documentation, but please note that the FPGA board has to be purchased separately. The reference design can also be made available as an accelerator function for Cloud FPGA instances using Accelize’s QuickStore. For more information please contact CAST sales.