Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG LS
Encoder
Lossless & Near-Lossless

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • Intel Accelerator
    • Xiinx PCIe Board

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
40G UDPIP Stack
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN PHY Daughter Card
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
IEEE 802.1AS Hardware
   Protocol Stack

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

  • PCIe board data compression reference design for ZipAccel-C Core evaluation or application development.

GZIP Acceleration

  • 40 Gbps (or higher upon request) uncompressed data rate
  • High compression efficiency (comparable to software gzip-6)
  • Fully Compliant to the GZIP  standard (RFC-1952)

Supported Hardware

  • Intel Programmable Acceleration Card (Intel PAC) with Intel Arria 10 GX FPGA
  • Bitware A10PL4 (Intel Arria 10)
  • Reflex CES XpressGXA10-LP1150B (Intel Arria 10)
  • Cloud FPGA instances vie      Accelize’s QuickStore
  • Design portable to other boards and FPGA families

Software Interface

  • Intel DCP Drivers
  • QuickPlay API
  • Works with libraries and frameworks using Intel Xeon Acceleration Stack for Xeon CPU with FPFAs

 

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

Info on Intel Xeon with FPGA:

CAST IP Cores:

News Releases

Applicable Standards

GZIP-RD-A10 PCIe GZIP Compression Acceleration Card Reference Design

The GZIP-RD-A10 is a reference design for an FPGA PCIe data compression acceleration card. It uses the ZipAccel-C GZIP/ZLIB/Deflate Compression IP Core, and has been designed with QuickPlay® in partnership with Accelize®.

The GZIP accelerator is highly efficient and can compress data at rates exceeding 40 Gbps, making it suitable for servers or databases where it optimizes storage requirements or network bandwidth.

The GZIP-RD-A10 is available as a ‘drop-in’ accelerator function for the Intel® Programmable Acceleration Card (Intel PAC) with Intel Arria 10 GX FPGA, as well as for Bitware’s A10PL4 and Reflex’s XpressGXA10-LP1150B FPGA boards. Different PCIe FPGA boards hosting an Arria10 FPGA device can be supported upon request.

The reference design is delivered with a sample GUI-driven application, which designers can use to evaluate the performance of the ZipAccel-C core or as a basis to develop their own application. Intel’s DCP drivers and the easy-to-use QuickPlay API facilitate integration with application software. The reference design pulls in frameworks and libraries using the Intel Acceleration Stack for Intel Xeon CPU with FPGAs, easing the use of FPGA acceleration in Xeon-based systems.

gzip-rd-a10 block diagram and reference board

The accelerator’s compression engine, the ZipAccel-C IP core, is highly configurable and can be tuned to meet different application requirements with respect to compression efficiency for specific data-types, latency and throughput. CAST will work with you to define the ZipAccel-C configuration that meets your application requirements. The reference design using a typical ZipAccel-C configuration can be evaluated at https://www.fpga-as-a-service.com/.

Deliverables include the firmware (FPGA programming file), software (drivers), and comprehensive documentation, but please note that the FPGA board has to be purchased separately. The reference design can also be made available as an accelerator function for Cloud FPGA instances using Accelize’s QuickStore. For more information please contact CAST sales.

 

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