- Based on Intel’s 80C152 Global Serial Channel
- Flexible addressing schemes
- Single and double byte address recognition
- Address filtering allowing multicast and broadcast addresses
- 16-bit CCITT or 32-bit frame check sequence
- NRZ or NRZI data encoding
- Full or half duplex operation
- Automatic bit stuffing/stripping
- 64-byte internal receive and transmit FIFOs (larger FIFOs available)
- External or internally generated transmit and receive clocks
- Optional preamble generation
- Programmable interframe space
- Raw transmit and receive testing modes
Communication IP Core SDLC Global Serial Channel Controller Core
The SDLC controller is a synthesizable HDL core of a high-speed synchronous serial communication interface.
Operation of the controller is similar to that used in the Intel 8XC152 Global Serial Channel (GSC) working in SDLC mode under a CPU control. Communication with the CPU is realized through Special Function Registers (SFRs) and 3 interrupt sources. This allows the SDLC controller to be easy integrated with any CPU core.
The design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset.
See representative implementation results (each in a new pop-up window):
The SDLC can be utilized for a variety of synchronous serial communication interface applications including:
- ISDN D-channel
- X.25 networks
- Frame Relay networks
- Custom serial interfaces
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The SDLC core can be modified to include features such as:
- Custom interfaces for external CPU
- Custom baud rate generation variants
- Variable size of internal FIFOs
The SDLC core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model that contained the original Intel 80C152 chip, and the results compared with the core’s simulation outputs.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Example testbench wrapper for post-route simulation
- Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide