Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Peripheral Platforms
& AMBA Infrastructure

BA2x AHB Platform
BA2x AXI Platform


See Peripherals Cores >

These video and image compression cores and subsystems help you handle video compression for demanding, high-quality applications or choose the best type of image compression for your specific system.

JPEG 2000
J2K Platform

Lossless Image Compression
LJPEG Encoder
LJPEG Decoder
JPEG-LS Encoder

Lossless Data Compression
GZIP Compressor
GZIP Reference Design
GUNZIP Decompressor

Complement or replace system processors with GPUs and easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers

NOR Flash Controllers
Serial/SPI NOR Flash
Parallel NOR Flash

Legacy Peripherals
DMA Controllers
8237, 82380
16450S, 16550S, 16750S

AMBA Infrastructure
AMBA Infrastructure Cores
Multi-Channel DMA

Interconnect Peripherals

See Interconnect Cores >

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
Hardware RTP Stack for H.264
• MPEG Transport Stream Encapsulator

Data Link Controllers

PCI — Target
32-bit multi
PCI — Master
32-bit multi
PCI — Host Bridge
32 bit
32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

DES single
DES triple

  • Controller for both the SDLC and HDLC (ISO 13239) transmission protocols
    • Based on the Intel 8XC152 Global Serial Channel (GSC), operating in SDLC Mode
    • Additional features support HDLC and proprietary serial protocols.
  • Flexible Frame Formatting
    • Programmable preamble pattern and preamble length
    • Programmable inter-frame space
    • Single- or double-byte address field
    • Address filtering allowing multicast and broadcast
    • Raw transmit and receive testing modes
    • Back-to-back transmit & back-to back receive
    • NRZ, NRZI, Bi-Phase-S, and Manchester Data Encoding
    • Bit Stuffing and Bit Stripping
    • 16-bit (CRC-16, CCITT or IBM) and 32--bit (CRC-32) frame check sequence
    • CRC, Bit-stuffing/stripping, and abort and idle sequences detection can be independently enabled/disabled
  • Flexible Serial Link Interface
    • Full or Half Duplex
    • Programmable Baud Rate
    • Modem Controls (RTSn/CTSn)
    • Collision detection
    • Internal baud generator, or external transmit clock with strobe
    • Automatic receive clock recovery, or external receive clock with strobe
  • Easy to Integrate
    • Suitable for interrupt-based or polling-based operation
    • Configurable size, Transmit & Receive FIFOs
    • 80xc152-like control-status registers
    • APB or Generic MCU-like Host Interface

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PDF Datasheets

Altera, Xilinx

HSDLC HDLC & SDLC Protocol Controller Core

The HSDLC IP core implements a controller for the High-Level Data Link Control (HDLC) and the Synchronous Data Link Control (SDLC) protocols. It is based on the Intel 8XC152 Global Serial Channel (GSC) working in SDLC mode, and adds features to support HDLC or proprietary frame transmission under host processor control.

HSDLC Block DiagramThe core operates as a peripheral to a host processor, and is easy to integrate with both modern and legacy processors. Control and status registers are accessible via an APB or a generic 80c51-like bus interface, and a comprehensive set of interrupt signals facilitates interrupt-based operation.


The controller’s great flexibility enables a variety of serial link setups. It provides two independent interfaces, one for transmitting and one for receiving data. Both interfaces provide control signals for the link drivers to support both full- and half-duplex operation. The controller can be programmed to use hardware flow control signals (RTS/CTS) and it can also detect collisions. The baud-rate is programmable and limited only by the link drivers and the core’s clock frequency. The core derives the receive clock from the received serial data, or uses an externally provided receive clock.

The HSDLC controller core is designed for reuse and is rigorously verified and scan-ready. Although designed to manage serial links, the core contains no latches or tri-states, and is fully synchronous with a single clock domain. The core is available in Verilog RTL or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation.

See representative implementation results (each in a new pop-up window):

ASIC numbers Altera numbers Xilinx numbers


The HSDLC controller core be used in telecommunication equipment supporting HDLC-based protocols such as X.25 or ISDN-D. It can also be used to implement serial interfaces between processors and peripherals.


The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.


The HSDLC core has been verified through extensive simulation and rigorous code coverage measurements.


The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:


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