Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

Processor Peripherals
AHB 32-bit DMA
AMBA Infrastructure Cores

Legacy Processors
See Legacy Cores >

These video and image compression cores help you handle video compression for demanding, high-quality applications or choose the best type of image compression for your specific system.

JPEG 2000
Encoder
J2K Platform

Block/Raster Converters
block-to-raster
raster-to-block
raster-block bidirect

Lossless Compression
LJPEG Encoder
LJPEG Decoder
JPEG-LS Encoder

Functions & Converters
Color Space Converter

Video Deinterlacers
Basic

Quickly complete the standrd parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores. Choose high-speed DisplayPort or PCI Express, Ethernet MACs, the CAN bus for automotive systems, and more.

High-Speed Serial
PCI Express
Family Overview
x1/x4
x8
application interface

Parallel
ECP slave
ATA/IDE interface

PCI — Target
32-bit
32-bit multi
64-bit
PCI — Master
32-bit
32-bit multi
64-bit
PCI — Host Bridge
32 bit
32 bit - AHB
32 bit & device - AHB

TCP/IP Stacks
UDP/IP stack

Ethernet MAC
Device Controllers

10/100
10/100 lite
Gigabit
Gigabit lite
Gigabit PCS

MAC Platforms
MAC/PCI

Customers find these cores to be an excellent solution for preserving existing product board designs when critical chips are no longer available for purchase.

 
80186XL
80186EC
80188EC
80251
387L math

DSPs
32025 16-bit
32025TX 16-bit

 

 

Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Cores for integrating security, controlling devices and displays, and other SoC functions.

Device Controllers
smart card reader

IR Remote Controls
RC5
NEC

Audio Interfaces
I2S-SC
I2S-MC
SPDIF

  • LAPB/LAPD controlling machine providing
    • modulo 8 frame numbering
    • modulo 128 frame numbering
    • one- or two-byte addressing
    • automatically generated responses
  • Serial Peripheral Interfaces
    • Bit stuffing
    • BOF and EOF flags generation
    • Support for RTS/CTS modem lines
    • Support for CD modem line
    • Collision detection in bus configuration
  • Receive Length Check
  • Three modes of receive operation
    • auto mode (with address recognition and control field insertion)
    • non-auto mode (with address recognition)
    • transparent mode (without address recognition)
  • Receive and transmit blocks
    • Interrupt transfer mode
    • DMA transfer mode
  • Separate FIFO’s
    • 64-bytes long receive FIFO
    • 64-bytes long transmit FIFO
    • 16-bytes long address FIFO for storing up to 16 small frames in the receive FIFO
  • Single or dual independent channel versions
    • Separate DMA lines for each channel
    • Common data bus and interrupt line
  • Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)

Configurability

  • Two top-level architectures allowing implementing single or double channel cores available.

Contact Sales
Call or click.
+1 800.391.8300

PDF Datasheets

ASIC
Altera, Xilinx

Related Products

  • SDLC Global Serial Channel Controller

Related Information

Validated for Mentor Graphics Presicision FPGA SynthesisValidated for Precision™ FPGA Synthesis

Communication IP Core HDLC HDLC Protocol Controller Core

The HDLC core implements a single- or dual-channel controller for the High-Level Data Link Control (HDLC) protocol and its derivates such as the Link Access Procedure, Balanced (LAPB) and Link Access Procedure, D channel (LAPD).

LAPB is used for public networks employing the X.25 communications protocol. LAPD is for ISDN applications.

The functional features of the core are based on the Siemens HSCX 82525 chip. Programs written for that chip can be used with the core with only minor changes.

The design is strictly synchronous with positive-edge clocking, no internal tri-states and with a synchronous reset; therefore scan insertion is straightforward.

 

See representative implementation results (each in a new pop-up window):

ASIC numbersAltera numbersXilinx numbers

Applications

The core can be used for a variety of interface and communications applications, including:

Block Diagram

hdlc block diagram

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

 

Share this page:

Twitter LinkedIn Add This: more sharing options
Top of Page

Follow CAST:

go to our SlideShare page