Communication IP Core HDLC HDLC Protocol Controller Core

The HDLC core implements a single- or dual-channel controller for the High-Level Data Link Control (HDLC) protocol and its derivates such as the Link Access Procedure, Balanced (LAPB) and Link Access Procedure, D channel (LAPD).

LAPB is used for public networks employing the X.25 communications protocol. LAPD is for ISDN applications.

The functional features of the core are based on the Siemens HSCX 82525 chip. Programs written for that chip can be used with the core with only minor changes.

The design is strictly synchronous with positive-edge clocking, no internal tri-states and with a synchronous reset; therefore scan insertion is straightforward.

See representative implementation results (each in a new pop-up window):

Applications

The core can be used for a variety of interface and communications applications, including:

• X.25 link control
• ISDN applications
• Physical link maintenance and quality monitoring of wide-area networks
• General purpose telecommunication applications

Block Diagram

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (soft core) or a post-synthesis EDIF netlist (firm core)
  
• An example single-channel design
  
• Sophisticated self-checking Testbench (Verilog versions use Verilog 2001) that instantiates example design, test bench environmental design, external DP RAM, clock generator, and monitors that compare simulation results with expected results
  
• Simulation script, vectors, expected results, and comparison utility; 
• Synthesis (soft) or place and route (firm) script
  
• Comprehensive user documentation, including detailed specifications and a system integration guide

This core is sourced from the IP experts at Evatronix SA.