CAST HDLC Core — ASIC Implementation Results

Optimized for area with constrains set at clk=50 MHz.

Channels

ASIC Technology

Approx. Area (gates)

Clock Constraint

Frequency

Single

TSMC  0.09 um

11,300

50 MHz

216 MHz

Single

TSMC  0.13 um

11,900

50 MHz

160 MHz

Dual

TSMC  0.09 um

26,917

100 MHz

100 MHz

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