Xilinx results configured with a buffer size of 64x30 bits implemented using a DPRAM.
Xilinx Device |
Slices |
BRAM | I/Os | Fmax |
ISE |
| Spartan-3E XC3S1200E-5 |
526 | 1 | 82 | 80 | 12.2i |
| Spartan-6 XC6SLX75-3 |
213 | 1 | 82 | 120 | 12.2i |
| Virtex-5 XC5VLX110-3 |
357 | 1 | 82 | 200 | 12.2i |
| Virtex-6 XC6VLX130T-3 |
229 | 1 | 82 | 226 | 12.2i |