I2S IP Core I2S-SC Inter-IC Sound Bus Controller Core

This I2C audio bus controller IP core implements an optimized, configurable, single-channel Inter-IC Sound (I2S) interface that combines both transmitter and receiver functions.

The core is compatible with the Philips I2S specification and all its modes. Instead of using eight channels, it more efficiently requires just one channel and uses time Division Multiplexing (TDM) for multi-channel communication.

A wide range of configurable transmission parameters add flexibility and allow for extending the core's functionality beyond the I2S standard. These include serial clock and word select polarities, audio channel width, data delay, the size of external FIFO, and the sample bits order. An included tool makes configuration simple.

The core supports the universal OCP socket interface, with various wrappers available for other system buses, such as AMBA® AHB and APB, or CoreConnect™ PLB. The core builds on a previous version that has been successfully fabricated in ASICs and FPGAs by multiple CAST customers.

See representative implementation results (each in a new pop-up window):

Applications

The I2S-SC core can be used in a variety of Inter-IC Sound (I2S) bus interface controller applications, including:

• ASIC and SoC applications requiring single channel audio data transmission
• Connecting Analog to Digital and Digital to Analog converters with very low jitter
• Digital audio interface of embedded microcontroller systems
• Error correction for compact disc and digital recording
• Digital signal processing and multimedia systems in general

Block Diagram

Support

The core, as delivered, is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, beginning with the first interaction. Additional maintenance and support options are available.

Verification

Functional verification of the synthesizable core was performed with a VHDL/Verilog testbench. The top level testbench contains a synthesizable module of the I2S-SC core and additional environment modules such as stimulus vectors, generator, and output vectors comparator.

Formal verification was performed for OCP, AMBA AHB, and APB interfaces and wrappers. Hardware verification of the prototype was performed with a FPGA board running a sample application.

Example Application

The example application consists of the following IP cores:

• ATAIF – Parallel ATA controller
• I2S controller CPU (C68000 microprocessor)
• The CPU working as the Data Processing Unit reads audio data from the CD-ROM through the ATAIF. It then writes the data to the single channel I2S-SC core. The I2S-SC core transfers these data to speakers with an I2S interface.

Configurability

A Design Configurator tool is available to help in the selection of the core’s many options. The configurable options include:

• Serial clock (SCK) polarity
• Word select (WS) polarity
• Frame synchronization / word select mode
• Audio channel width
• Data delay
• Data align within audio channel and host data bus
• Sample bit order
• Audio/mono mode
• Time Division Multiplexing (TDM) implementation
• Size of external FIFO (default value is 16 words)
• Width of data registers – maximum audio data width
• Host-side interface type
• Width of host data buses
• Size of external FIFO (default value is 16 words)

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• VHDL or Verilog source code (soft core) or a post-synthesis EDIF netlist (firm core)
• An example I2S-SC chip implementation
• Sophisticated HDL Testbench including external FIFOs, buffers, clock generators, and models of interfaces
• Simulation script, vectors, expected results, and comparison utility
• Synthesis (soft) or place and route (firm) script
• Comprehensive user documentation, including detailed specifications and a system integration guide

This core is sourced from the IP experts at Evatronix SA.