Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

Processor Peripherals
AHB 32-bit DMA
AMBA Infrastructure Cores

Legacy Processors
See Legacy Cores >

These video and image compression cores help you handle video compression for demanding, high-quality applications or choose the best type of image compression for your specific system.

JPEG 2000
Encoder
J2K Platform

Block/Raster Converters
block-to-raster
raster-to-block
raster-block bidirect

Lossless Compression
LJPEG Encoder
LJPEG Decoder
JPEG-LS Encoder

Functions & Converters
Color Space Converter

Video Deinterlacers
Basic

Quickly complete the standrd parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores. Choose high-speed DisplayPort or PCI Express, Ethernet MACs, the CAN bus for automotive systems, and more.

High-Speed Serial
PCI Express
Family Overview
x1/x4
x8
application interface

Parallel
ECP slave
ATA/IDE interface

PCI — Target
32-bit
32-bit multi
64-bit
PCI — Master
32-bit
32-bit multi
64-bit
PCI — Host Bridge
32 bit
32 bit - AHB
32 bit & device - AHB

TCP/IP Stacks
UDP/IP stack

Ethernet MAC
Device Controllers

10/100
10/100 lite
Gigabit
Gigabit lite
Gigabit PCS

MAC Platforms
MAC/PCI

Customers find these cores to be an excellent solution for preserving existing product board designs when critical chips are no longer available for purchase.

 
80186XL
80186EC
80188EC
80251
387L math

DSPs
32025 16-bit
32025TX 16-bit

 

 

Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Cores for integrating security, controlling devices and displays, and other SoC functions.

Device Controllers
smart card reader

IR Remote Controls
RC5
NEC

Audio Interfaces
I2S-SC
I2S-MC
SPDIF

  • Meets Philips Inter-IC Sound Bus Specification
  • Supported modes
    • I2S Philips
    • Left Justified
    • Right Justified
    • DSP
    • Time Division Multiplexing (TDM)
  • Two clock domains
    • Host side clock domain
    • System clock for the I2S channel
  • One wide-configurable stereo channel with up to 16 optional channels with TDM support
  • Set of SCK (SCLK) and WS (LRCLK) strobes
  • A number of possible host-side slave interfaces for data and configuration:
    • OCP™ slave interface
    • AMBA® APB
    • AMBA® AHB
    • CoreConnect™ PLB
  • Contains configurable FIFO buffer for transmission channel
  • Interrupts driven by the I2S bus activity events
  • Handshake interface to external DMA modules
  • Extensive core configurability: choose options as needed, or use fully-configurable version
  • I2S-SC consists of:
    • OCP™ compliant slave interface
    • Optional AMBA® APB, AMBA® AHB or CoreConnect™ PLB bus wrapper
    • Transmission FIFO controller
    • Special Function Registers block (SFR)
    • Single channel I2S half-duplex transceiver

Contact Sales
Call or click.
+1 800.391.8300

PDF Datasheets

ASIC
Altera, Xilinx

Related Products

  • I2S-MC Multi-Channel Inter-IC Sound Bus
  • SPDIF-APB Digital Audio Interface

Related Information

Our Blog Post
New I2S Audio Interface IP Core Great for High-Def Sound

Articles

WHATIS.COM - definition

EDUCYPEDIA - I2C and I2S links to spec, FAQs, etc.

I2S IP Core I2S-SC Inter-IC Sound Bus Controller Core

This I2C audio bus controller IP core implements an optimized, configurable, single-channel Inter-IC Sound (I2S) interface that combines both transmitter and receiver functions.

The core is compatible with the Philips I2S specification and all its modes. Instead of using eight channels, it more efficiently requires just one channel and uses time Division Multiplexing (TDM) for multi-channel communication.

A wide range of configurable transmission parameters add flexibility and allow for extending the core's functionality beyond the I2S standard. These include serial clock and word select polarities, audio channel width, data delay, the size of external FIFO, and the sample bits order. An included tool makes configuration simple.

The core supports the universal OCP socket interface, with various wrappers available for other system buses, such as AMBA® AHB and APB, or CoreConnect™ PLB. The core builds on a previous version that has been successfully fabricated in ASICs and FPGAs by multiple CAST customers.

See representative implementation results (each in a new pop-up window):

ASIC numbers Altera numbers Xilinx numbers

Applications

The I2S-SC core can be used in a variety of Inter-IC Sound (I2S) bus interface controller applications, including:

Block Diagram

i2s-sc block diagram

Support

The core, as delivered, is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, beginning with the first interaction. Additional maintenance and support options are available.

Verification

Functional verification of the synthesizable core was performed with a VHDL/Verilog testbench. The top level testbench contains a synthesizable module of the I2S-SC core and additional environment modules such as stimulus vectors, generator, and output vectors comparator.

Formal verification was performed for OCP, AMBA AHB, and APB interfaces and wrappers. Hardware verification of the prototype was performed with a FPGA board running a sample application.

Example Application

The example application consists of the following IP cores:

i2sc-sc example application

Configurability

A Design Configurator tool is available to help in the selection of the core’s many options. The configurable options include:

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

 

Share this page:

Twitter LinkedIn Add This: more sharing options
Top of Page

Follow CAST:

go to our SlideShare page