- Meets Philips Inter-IC Sound Bus Specification
- Supported modes
- I2S Philips
- Left Justified
- Right Justified
- Two clock domains
- APB the host side clock domain
- system clock for the I2S channels
- Eight configurable stereo channels
- Two sets of SCK (SCLK) and WS (LRCLK) strobes
- one for all transmitters
- one for all receivers
- AMBA™ APB bus slave interface for data and configuration
- Contains two configurable FIFO buffers
- one for all transmit channels
- one for all receive channels
- One configuration register block for all channels
- Interrupts driven by the I2S bus activity events
- Handshake interface to external DMA modules
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
- Synthesis parameters allow adjustment to the target application
I2S IP Core I2S-MCMulti-Channel Inter-IC Sound Bus Core
The I2S-MC core integrates eight channels of Inter-IC Sound compatible serial buses. I2S is a well-known stereo audio transmission standard, widely used to connect system elements such as Analog to Digital and Digital to Analog converters.
By using the I2S-MC module in a SoC design, a designer can easily integrate the core used for multi-channel audio transmission with the master system based on a standard AMBA APB bus for further data processing. In order to facilitate the use of the I2S core in AMBA bus based microprocessor systems, it is provided with an AMBA™ APB bus wrapper, transmit and receive FIFO control units, special function registers block (SFR), and 8-channels of the I2S core.
The data collected by the I2S-MC core is stored in the core’s internal FIFO. This use of an internal FIFO allows the system to process the relatively slow audio stream in the interrupt-triggered subroutines.
The collected data can then be easily and quickly accessed by the master system by the AMBA APB bus by any APB bus master.
Developed for reuse in ASIC and FPGA implementations, the design is strictly synchronous with two clock domains, positive-edge clocking in both domains (except of four flip-flops for reset signal synchronization). There are no internal tri-states and asynchronous resets, therefore scan insertion is straightforward.
See representative implementation results (each in a new pop-up window):
The I2S-MC can be utilized for a variety of Inter-IC Sound compatible serial bus applications including::
- ASIC and SoC applications requiring up to 8 channel audio data transmission
- Connecting Analog to Digital and Digital to Analog converters with very low jitter
- Digital audio interface of embedded microcontroller systems
- Error correction for compact disc and digital recording
- Digital signal processing and multimedia systems in general
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Functional verification of synthesizable core is performed with a Verilog testbench. The top level of testbench contains synthesizable block of I2S-MC core and additional environment modules like stimulus vectors generator and output vectors comparator.
Hardware verification of the prototype was realized with the aid of application demo. This application was developed on proprietary EB-3 Demo Board.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- Verilog 2001 RTL source code (soft core) or a post-synthesis EDIF netlist (firm core)
- Example design for I2S-MC (CHIP_I2S_MC)
- Sophisticated Verilog 2001 self-checking Testbench
- Simulation script, vectors, and expected results
- Synthesis (soft) or place and route (firm) script
- Comprehensive user documentation, including detailed specifications and a system integration guide