T8051XC3 Core ASIC Implementation Results

The T8051XC3 can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample ASIC pre-layout results. They do not represent the absolute highest speed or smallest area possible. (Area figures do not include memories.) . Please contact CAST to get characterization data for your target configuration and technology.

 

Technology

Clock Frequency

Area

T8051XC3–CPU (CPU-only)
180nm
39 MHz
3,500 eq. Gates
T8051XC3  (CPU, peripherals, no-OCDS)
180nm
39 MHz
6,300 eq. Gates
T8051XC3  (CPU, peripherals, no-OCDS)
180nm
175 MHz
10,100 eq. Gates
T8051XC3–CPU (CPU-only)
90nm
107 MHz
3,500 eq. Gates
T8051XC3  (CPU, peripherals, no-OCDS)
90nm
103 MHz
6,400 eq. Gates
T8051XC3  (CPU, peripherals, no-OCDS)
90nm
476 MHz
10,600 eq. Gates

 

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