S8051XC3 Core ASIC Implementation Results

The S8051XC3 can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The tables below provide sample performance and resource utilization data. Please contact CAST to get characterization data for your target configuration and technology.

First are sample Dhrystone 2.1 benchmarks. The Dhrystone 2.1 benchmark score varies from 0.088 to 0.252 DMIPS/MHz, which translates to speed improvements from 9.4 to 26.85 times over the standard 80C51 assuming the same clock frequency, or 350x to more than 1,000 times increase when the S8051XC3 is clocked at 450MHz.

Version

DMIPS/MHz

80C51 Ratio

S8051XC3-F

0.252

26.8

S8051XC3-C

0.147

15.6

S8051XC3-A

0.088

9.4

Next are sample results for the cores CPU using a 90nm ASIC technology.

Version

Maximum Speed

Minimum Area

S8051XC3-F

355 MHz

11.5k gates

S8051XC3-C

395 MHz

9.3k gates

S8051XC3-A

475 MHz

6.2k gates

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