R8051XC2 Core — ASIC Implementation Results

TheR8051XC2 can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample results using a 90nm ASIC technology, and separate optimizations for speed and area. The EASE debug option is not included. Please contact CAST to get characterization data for your target configuration and technology.Reference designs have been evaluated in a variety of technologies.

Version & Configuration Maximum Speed Minimum Area
(CPU – only)
450 MHz 8.0k gates
(CPU + peripherals + OCDS) 270 MHz 70.7k gates

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