- Fully compatible with the MCS® 51 instruction set
- Single clock per cycle and efficient architecture for up to 12.1 times the performance of original 8051
- Fewer machine cycles means lower average power usage in most applications
- Extensive set of optional features and peripherals: choose configurable or less-expensive fixed versions
- Debugging option: On-Chip Debug Support (OCDS) block that interfaces through IEEE1149.1 (JTAG) port; external debugging pod with JTAG and single-wire SWAT; and debugging software with interface to Keil & IAR tools
Options and Peripherals
Full user-configurable version includes all of these; other versions include a subset (see Versions).
External Memory Interface:
- Addresses up to 8 MB of Program and Data Memory each (when using
- One, two or eight Data Pointers for fast data block transfer
- Additional Arithmetic Unit supports data pointers, auto-increment/-decrement,
- Supports external DMA controller through HOLD function
- Program memory write mode
Direct Memory Access (DMA) Controller:
- Up to eight independent channels
- Read/Write Access to all memory spaces (incl. SFR)
- Linear addressing (up to 8MB)
- Address auto-increment/decrement
- Synchronous/asynchronous Mode
- Software/Hardware Triggers
- 16 x 16-bit multiplication,
- 32/16- and 16/16-bit division,
- 32-bit normalization and L/R shifting
Special Function Registers Interface:
- services from 36 to 119 external SFRs
- Four priority levels with eighteen interrupt sources, or
- Two priority levels with six sources
- Parallel Ports: up to four 8-bit Input/Output ports
- Serial 0 interface:
- Full-duplex serial interface (80C51-like),
- Equipped with an additional baud rate generator
- Serial 1 interface:
- an asynchronous-only version of Serial 0
- SPI Master/Slave interface
- I2C™ Master/Slave interfaces: one or two
Timers and Counters
- 16-bit Timers/Counters:
- Timers 0 and 1: 80C51-like simple timers
- Timer 2: 80C515-like, operates as timer, event counter or gated timer
- Watchdog Timer: 15-bit programmable
Power Management Unit with power-down modes (IDLE/STOP)
- all versions include sophisticated self-checking Testbench (Verilog versions use Verilog 2001) with CPU behavioral model, memory models, and more.
Call or click.
The 8051 family also includes:
- S8051XC3 Super-Fast 8051 Microcontroller Core with Configurable Features and Peripherals
- L8051XC1 Legacy-Configurable 8051-Compatible Microcontroller IP Core
Options for this Core
Several versions of this 8051 core are available; see below.
A native on-chip debug package with external adapter (pod) is available for JTAG or single-wire SWAT debugging, with support for Keil and IAR tools.
Try It Yourself
Evaluate the R8051XC2's features and performance in your own environment with the Talos Series Evalation Kit.
- 05/28/14, CAST 8051 IP Subsystem for CAN FD Transceiver Development Utilized by ON Semiconductor
- 03/19/14, GIT Japan Uses CAST 8051 in AIST’s MEMS-EFS Electrostatic Sensor
- 12/20/13, CAST Partners with Silesia Devices for Superior 8051 Microcontroller IP Cores
- 03/12/13, CAST ‘s 200th 8051 IP Core License Goes to Ensphere Solutions
- 05/30/12, 8051 Microcontroller IP Cores from CAST Even More Efficient with New Single-Wire Debug
- 04/26/12, CAST’s Talos Evaluation Kits Help Designers Choose the Best Microcontroller/Processor IP Cores
- 01/11/12, Kawasaki Microelectronics Licenses CAST 8051 IP Core for New Design Platform
- 01/21/09, CAST Releases Fastest 8051 IP Core
Understanding Interrupt Latency in Modern 8051s by Nikos Zervas at ChipEstimate.com
CAST Announces World's Fastest 8051-Compatible MCU Core by Max Maxfield, EE Times
CAST’s 8051 IP core is going strong
Article by Clive Maxwell, EE Times
Using 8-bit 8051s in a 32-bit World
Article by Bill FInch, in Extension Media's Engineers' Guide to 8/16-bit Technologies
- Gabrielle Saucier Interviews Hal Barbour at D&R IP SoC Grenoble 2014
- 8051 Interrupt Latency: Designing with Modern 8-bit MCUs
- 8051s at DesignCon: Survey Insights
- CAST Interviewed: "Examining the Enduring Appeal of the 8051"
- Cadence/Evatronix Acquisition News
- Webinar - CPU Subsystem Total Power Consumption: Understanding the Factors and Selecting the Best IP
- Power Time - GSA Blog Post & CAST Webinar
- Peggy Aycinena Interview — Hal Barbour: Master of the mega-trend
- 8051s in the Spectrum of Microcontroller Choices
- 8051 IP Cores Still Going Strong
The R8051XC2 is supported by leading development and debug tools, including:
Develop software for this 8051 core with the ARM® Keil™ µVision4 Integrated Development Environment
"The µVision®4 IDE builds on the success of what is widely acknowledged as the most popular development environment for microcontrollers," said Mark Onions, Director of Marketing, System Design Division at ARM. "Now, with support for the R8051XC2 processor, developers using the 8051 architectures can benefit from faster hardware and software development and verification." 8/10/09
R8051XC2 High-Performance, Configurable, 8051-Compatible, 8-bit Microcontroller Core
This 8051 IP core implements a range of fast, 8-bit, 8051-compatible microcontrollers that execute the MCS®51 instruction set.
The R8051XC2 IP core runs with a single clock per machine cycle, and requires an average of 2.12 machine cycles per instruction. Dhrystone 2.1 tests show it to run from 9.4 to 12.1 times faster than the original 8051 at the same frequency. Representative 90 nm ASIC results have reached 430 MHz, for an effective speed-up of 400 times over 80C51 chips.
The configurable core has a rich set of optional features and peripherals. Designers can choose from several versions, including the easy-to-configure full version with all options included; a custom, non-configurable version with options specified at purchase; and pre-packaged versions with different sets of options and degrees of configurability.
All versions of this 8051 core benefit from power-saving architectural efficiency—the R8051XC2 is 10% better in milliwats/DMIP than our previous generation—and various power-management options are available. System development is facilitated through a native on-chip debugging option and support by development tools from Keil and IAR.
This product builds on CAST’s experience with hundreds of 8051 IP customers going back to 1997. Designed for easy reuse in ASICs, structured ASICs, or FPGAs, the core is strictly synchronous, with positive-edge clocking (except in the optional debug & SPI modules), synchronous reset, and no internal tri-states. Representative 90nm ASIC results show the core to be conservative in its use of space, requiring just 8,000 to 71,000 gates.
See representative implementation results (in a new pop-up window):
The 8051 continues to be a rigorous and cost-effective solution for many
applications, and the fast, flexible R8051XC2 is an especially good choice
for many systems. Popular uses include data management control for complex
systems, and interface control for analog and sensing chips.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available; contact CAST Sales.
The core has been verified through extensive simulation and rigorous code coverage measurements. All subcomponents were functionally verified with an HDL testbench using their individual test suites. The CPU and ALU have been verified against a proprietary hardware modeler and behavioral models. The peripherals have also been verified in their own testbenches, based on either hardware or behavioral models. An extensive constrained random verification was performed to verify the CPU, DMA and OCDS.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Easy-to-use configuration tool (with configurable versions)
- An example chip implementation, which uses the core in a sample system
- Sophisticated self-checking HDL Testbench including everything needed to test the core (Verilog versions use Verilog 2001)
- Simulation script, vectors, and expected results
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
A reference design board is available; contact CAST Sales for information.
Three versions of this 8051 core are available, offering a range of capabilities and prices. (See block diagrams below.)R8051XC2-F includes the full set of options, and is user-configurable (i.e., options may be included or excluded prior to synthesis).
R8051XC2-A includes options that match the original Intel 8051 peripheral set: 64kB memory interface, two timers, one serial port, four parallel I/O Ports, two-level interrupt controller, and two DPTR registers. These options are user-configurable (i.e., may be deleted prior to synthesis).
R8051XC2-B includes options that match the Infineon 80515/80517 peripheral set: 64kB memory interface, three timers, two serial ports, four parallel I/O ports, watchdog timer, multiplication-division unit, and two DPTR registers. These options are user-configurable (i.e., may be deleted prior to synthesis).
ASIC (RTL) and FPGA (netlist) deliverables are available; FPGA packages are not user-configurable.
Block Diagrams for Standard Versions
R8051XC2-F Block Diagram
R8051XC2-A Block Diagram
R8051XC2-B Block Diagram