The following results use typical conditions, exclude memories, and were optimized for the clock speeds shown.
| ASIC Technology |
Cell Area | NAND2 Area | Approx. Area | Frequency |
| TSMC 0.09µ TSMC 0.13µ TSMC 0.18µ |
25,439 50,338 101,262 |
2.8224 5.0922 9.9792 |
9,013 gates 9,885 gates 10,147 gates |
350 MHz 300 MHz 250 MHz |
Configuration Notes: R8051XC-EP– 2 timers/counters; 1 serial interface; 2-priority/5-source interrupt controller. Does not include full on-chip debug: OCDS implemented with two hardware breakpoints will add about 5,000 gates.