- Control Unit
- Eight-bit instruction decoder for MCS® 51 instruction set
- Executes instructions with one clock per cycle (versus twelve for standard 80C51) for an average 8x speed up
- ALU performs 8-bit arithmetic, multiplication and division, and Boolean manipulations
- 32-bit Input/Output ports
- Four 8-bit I/O ports
- Alternate port functions such as external interrupts and serial interface are separated, providing extra port pins when compared with the standard 8051
- Two 16-bit Timer/Counters
- Interrupt Controller with two priority levels and five sources
- Internal Data Memory Interface can address up to 256 bytes of Read/Write Data Memory Space
- External Memory interface
- Can address up to 8 MB of External Program Memory and up to 8 MB of External Data Memory (when using memory banking)
- De-multiplexed Address/Data Bus for easy connection to memories
- Variable length MOVX to access fast/slow RAM or peripherals
- Wait cycles to access fast/slow ROM
- Dual data pointer register
- Program memory write mode
- Special Function Registers interface services up to 103 External SFRs
- Power Management Unit – IDLE and STOP modes
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
- EASE Debugging option: On-Chip Debug Support (OCDS) block that interfaces through IEEE1149.1 (JTAG) port; external debugging pod with JTAG and USB; and debugging software with interface to Keil C51 tools
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Options for this Core
EASE Debugging Support for CAST Processor Cores
The 8051 family includes:
- R8051XC2 High-Performance, Configurable, 8051-Compatible, 8-bit Microcontroller
- T8051 Tiny, 8051-Compatible, 8-Bit Microcontroller
- R80251XC Fast, Configurable, 80251-Compatible Microcontroller
Using 8-bit 8051s in a 32-bit World
Article by Bill FInch, in Extension Media's Engineers' Guide to 8/16-bit Technologies
CAST is the leading supplier of 8051-compatible IP cores.
8051 IP Core R8051XC-EP 8051-Compatible, Economical, 8-bit Microcontroller Core
This 8051 IP core is an economical, entry-point, fixed-configuration core that implements an 8051-like 8-bit microcontroller that executes all ASM51 instructions. It has the same instruction set as the 80C31, but executes operations an average of eight times faster.
The R8051XC-EP IP core provides hardware and software interrupts, an interface for serial communication, two timers, an Intel-compatible interrupt scheme, parallel I/O ports, and a power management unit.
The R8051XC-EP is one of our proven 8051 family of processor cores, which have been successfully implemented in a hundred different customer products. Representative ASIC implementation data shows it to offer competitive performance and area results, requiring for example about 9,000 gates for 350 MHz.
Developed for easy reuse in ASIC and FPGA implementations, the microcode-free design is strictly synchronous, with positive-edge clocking, no internal tri-states, and a synchronous reset. Scan insertion is straightforward. System development is facilitated through the EASE native on-chip debugging option and support by Keil’s C51 integrated development environment.
See representative implementation results (each in a new pop-up window):
The R051XC-EP is suitable as a primary or secondary controller in a wide variety of applications, including 8-bit data processing systems, mobile and other products requiring low power consumption, high-speed control systems, and mixed-signal SoC applications.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The R80515XC-A core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model that contained the original Intel 80C31 and Siemens SAB80C537 chips, and the results compared with the core’s simulation outputs. The core was also verified through extensive functional simulation, and has achieved high code coverage results. The core satisfies the requirements of the Reuse Methodology Manual and VSIA Quality IP Metric.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- An example implementation with sample system
- Sophisticated self-checking HDL Testbench including everything needed to test the core (Verilog versions use Verilog 2001)
- Simulation script, vectors, and expected results
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide