8051 IP Core R8051XC-EP 8051-Compatible, Economical, 8-bit Microcontroller Core

This 8051 IP core is an economical, entry-point, fixed-configuration core that implements an 8051-like 8-bit microcontroller that executes all ASM51 instructions. It has the same instruction set as the 80C31, but executes operations an average of eight times faster.

The R8051XC-EP IP core provides hardware and software interrupts, an interface for serial communication, two timers, an Intel-compatible interrupt scheme, parallel I/O ports, and a power management unit.

The R8051XC-EP is one of our proven 8051 family of processor cores, which have been successfully implemented in a hundred different customer products. Representative ASIC implementation data shows it to offer competitive performance and area results, requiring for example about 9,000 gates for 350 MHz.

Developed for easy reuse in ASIC and FPGA implementations, the microcode-free design is strictly synchronous, with positive-edge clocking, no internal tri-states, and a synchronous reset. Scan insertion is straightforward. System development is facilitated through the EASE native on-chip debugging option and support by Keil’s C51 integrated development environment.

See representative implementation results (each in a new pop-up window):

Applications

The R051XC-EP is suitable as a primary or secondary controller in a wide variety of applications, including 8-bit data processing systems, mobile and other products requiring low power consumption, high-speed control systems, and mixed-signal SoC applications.

Block Diagram

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The R80515XC-A core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model that contained the original Intel 80C31 and Siemens SAB80C537 chips, and the results compared with the core’s simulation outputs. The core was also verified through extensive functional simulation, and has achieved high code coverage results. The core satisfies the requirements of the Reuse Methodology Manual and VSIA Quality IP Metric.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• An example implementation with sample system
• Sophisticated self-checking HDL Testbench including everything needed to test the core (Verilog versions use Verilog 2001)
• Simulation script, vectors, and expected results
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide

This core is sourced from the IP experts at Evatronix SA.