- Single clock per machine cycle
- Up to 0.397 DMIPs/MHz
- More than 300MHz on 65nm
- Power Management Unit eases dynamic power management
- Higher performance allows doing more in less time and sleep for longer times, or operating in lower frequencies
- JTAG debugging via the optional OCDS module
- JTAG to USB debugging pod;
- Integration with Keil C251 tools
Options and PeripheralsFull user-configurable version includes all of these; other versions include a subset (see Versions).
- External Memory Interface with 24-bit linear address space of up to 16 MB of Program and Data Memory
- On-chip RAM Interface that services up to 1kB of memory
- Special Function Registers Interface: services from 43 to 115 external SFRs
- 40 bytes of Register File available as bytes, words or double words in a single clock cycle
- 8-byte instruction queue
- 64KB of extended stack space
- Two clock per cycle (legacy mode) supported
- Binary Mode (legacy 8051 compatibility) or Source Mode of operation (extended 80251 compatibility)
- Programmable wait-states for code and data memory
- Power Management Unit with power-down modes (IDLE/STOP)
- On-Chip Debug Support (OCDS)
- Parallel Ports: up to four 8-bit Input/Output ports
- Serial 0 interface: Full-duplex UART/USRT (80C51-like)
- Serial 1 interface: Full-duplex UART (80C517-like)
- Timers: up to three 16-bit timers (80C251-like)
- Programmable Counter Array
- Watchdog Timer: 14-bit programmable
- SPI Master/Slave interface
- One or Two I2C™ Master/Slave interfaces
- Real Time Clock
Call or click.
The 8051 family includes:
- R8051XC2 High-Performance, Configurable, 8051-Compatible, 8-bit Microcontroller
- R8051XC-EP 8051-Compatible, Economical, 8-bit Microcontroller
- T8051 Tiny, 8051-Compatible, 8-Bit Microcontroller
Options for this Core
EASE Debugging Support for CAST Processor Cores
80186EC IP Core R80251XC Fast, Configurable, 80251-Compatible Microcontroller Core
This 80251-compatible IP core implements a range of fast microcontrollers that execute the MCS® 251 instruction set and legacy code for the MCS® 51 instruction set.
The R80251XC IP core requires a single clock per machine cycle and runs an average of 3.18 times faster than the original 80C251 chip at the same clock frequency. Dhrystone 2.1 test results of 0.098 to 0.397 DMIPS/MHz (depending on features) show the core runs up to 41.8 times faster than the original 80C51 and up to 3.8 times faster than the 80C251 at the same clock frequency.
The core has a rich set of optional features and peripherals. Designers can choose from several versions, including the easy-to-configure full version with all options included and a variety of pre-packaged versions. System development is facilitated through the EASE native on-chip debugging option and support of Keil’s C251 integrated development environment.
This R80251XC builds on CAST’s experience with hundreds of 8051 IP customers go-ing back to 1997. The core is designed for easy reuse in ASICs, structured ASICs, or FPGAs, and it has been rigorously verified and production-proven.
See representative implementation results (each in a new pop-up window):
Legacy code support with faster performance makes the core suitable for economically developing new systems by extending existing systems with new capabilities.
Six versions of the core are available, offering a range of capabilities and prices.
R80251XC includes all options, and is user-configurable (options may be included or excluded prior to synthesis).
R80251XC-C includes a custom set of options specified by the customer, and is not user-configurable.
R80251XC-I includes options that match the original Intel 80C251 peripheral set: three timers, PCA, serial port, four parallel I/O Ports, two external interrupts, and a watchdog timer. These options are user-configurable (i.e., may be deleted prior to synthesis).
R80251XC-IF version derived from the R80251XC-I, but is fixed and not user-configurable.
R80251XC-T includes options that match the original Intel 80C251 with enhanced performance including: three timers, PCA, serial port, four parallel I/O Ports, two external interrupts, and a watchdog timer. These options are user-configurable (i.e., may be deleted prior to synthesis).
R80251XC-TF version derived from the R80251XC-T, but is fixed and not user-configurable.
ASIC (RTL) and FPGA (netlist) deliverables are available; FPGA packages are not user-configurable.
The native EASE debugging package is an extra option for all versions.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available; contact CAST Sales.
The core is available in ASIC (synthesizable HDL) or FPGA (netlist) forms, and includes everything required for successful implementation. ASIC versions include:
- HDL RTL source code
- Behavioral model
- Easy-to-use configuration tool (with configurable versions)
- An example chip implementation, which uses the core in a sample system
- Sophisticated self-checking HDL Testbench including everything needed to test the core (Verilog versions use Verilog 2001)
- Simulation script, vectors, and expected results
- Synthesis script
- Comprehensive user documentation, including detailed specifications and a system integration guide
A reference design board is available; contact CAST Sales for information.