CAST L8051XC1 Core — XILINX FPGA Results

The L8051XC1 can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following tables provide sample Xilinx results that are obtained after speed optimization during synthesis and place and route, while assuming that all core I/Os are routed off-chip. The provided figures do not represent the higher speed or smaller area for the core and area figures do not include any memories. . Please contact CAST to get characterization data for your target configuration and technology.

Table 1: Sample Implementation results for Spartan6-3

Configuration Logic Utilization
(Slices)
Fmax
(MHz)
L8051XC1-CPU
(CPU-only)
410 103
L8051XC1-A
(Timer 0 & 1, Serial 0, 4 parallel ports)
724 93
L8051XC1-CF
(Timer 0, 1 & 2, WDT, RTC, SPI, 2 I2C,  Serial 0 & 1, 4 parallel ports, MDU, DMA, 8 DPTRs, DPTR Arith, OCDS)
3,173 55

Table 2: Sample Implementation results for Artix7-3

Configuration Logic Utilization
(LUTs)
Fmax
(MHz)
L8051XC1-CPU
(CPU-only)
1,301 132
L8051XC1-A
(Timer 0 & 1, Serial 0, 4 parallel ports)
1,731 108
L8051XC1-CF
(Timer 0, 1 & 2, WDT, RTC, SPI, 2 I2C, Serial 0 & 1, 4 parallel ports, MDU, DMA, 8 DPTRs, DPTR Arith, OCDS)
9,782 77

 

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