L8051XC1 Core — ASIC Implementation Results

The L8051XC1 can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample ASIC pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip. The target technology is TSMC 40nm. The provided figures do not represent the higher speed or smaller area for the core and area figures do not include any memories. Please contact CAST to get characterization data for your target configuration and technology.


(Eq. KGates)



7,031 1,209
(Timer 0 & 1, Serial 0,4 parallel ports)
10,316 992
(Timer 0, 1 & 2, WDT, RTC, SPI, 2 I2C,  Serial 0 & 1, 4 parallel ports, MDU, DMA, 8 DPTRs, DPTR Arith., OCDS)
40,819 846

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