Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
40G UDPIP Stack
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN PHY Daughter Card
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
IEEE 802.1AS Hardware
   Protocol Stack

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

  • Fully compatible with the MCS® 51 instruction set
  • Configurable CPU architecture: 12, 6, or 4 clock cycles per machine cycle
  • Extensive set of optional features and peripherals
  • JTAG-based On-Chip Debug Support (OCDS)
  • Integration with IAR Embedded Workbench & Keil uVision™ IDEs

Options and Peripherals

A wide range of architectural options and peripherals is available for integration with the L8051XC1, and more peripherals can be developed on demand. The following is partial list of the off-the-shelf available peripherals:

  • External Memory Interface:
    • One, two or eight Data Pointers for fast data block transfer
    • Additional Arithmetic Unit supports data pointers, auto-increment/-decrement, and auto-switch
    • Supports external DMA controller through HOLD function
    • Program memory write mode
  • Direct Memory Access (DMA) Controller
  • Multiplication-Division Unit
  • 37 to 119 external Special Function Registers
  • Interrupt Controller with two or four priority levels, and six or eighteen interrupt sources
  • Up to five Parallel I/O Ports
  • Serial 0 full-duplex serial interface (80C51-like), equipped with an additional baud rate generator
  • Serial 1 (asynchronous-only version of Serial 0) interface
    SPI Master/Slave interface
  • One or two I2C™ Master/Slave interfaces
  • Timers 0, 1 and Timer 2 with Compare/Capture (80C515-like)
  • 15-bit programmable Watchdog Timer
  • Real Time Clock
  • Power Management Unit with power-down modes (IDLE/STOP)

 

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

The 8051 family also includes:

Compare
Versions

  • R8051XC2 High-Performance, Configurable, 8051-Compatible, 8-bit Microcontroller IP Core
  • S8051XC3 Super-Fast 8051 Microcontroller IP Core with Configurable Features and Peripherals
  • T8051XC3 Ultra-Small 8051-Compatible Microcontroller IP Core
  • S80251XC3 Super-fast, Configurable 16-bit 80251-compatible Microcontroller IP Core
  • T80251XC3 Tiny, Configurable, 16-bit 80251-compatible Microcontroller IP Core

Download our Controllers & Processors IP Overview (PDF).

Development Tools & Options

Coding and debug this 8051 with these popular IDEs:

These tools work with an optional, native on-chip debug block and inexpensive external adapter (pod) with a JTAG four-wire or SWAT Single-Wire PC interface.

evaluate CAST 32-bit processor IP cores with the Talos Eval KitEvaluation:
Try it for Yourself

Easily evaluate this 8051's features and performance in your own environment with the Talos Series Evaluation Kit.

Articles

Understanding Interrupt Latency in Modern 8051s by Nikos Zervas at ChipEstimate.com

CAST Announces World's Fastest 8051-Compatible MCU Core by Max Maxfield, EE Times

CAST’s 8051 IP core is going strong
Article by Clive Maxwell, EE Times

Using 8-bit 8051s in a 32-bit World
Article by Bill FInch, in Extension Media's Engineers' Guide to 8/16-bit Technologies

Blog Posts

See more 8051 blog posts >>>

L8051XC1Legacy-Configurable 8051-Compatible Microcontroller IP Core

The L8051XC1 core implements an MCS®51-compatible microcontroller that is specially designed to match the timing and peripherals of legacy 8051 MCU based systems.

8051 block diagram for super-fast IP core from CAST

The core can be configured to execute an instruction every 12, 6, or 4 clock cycles. Architectural extensions are user-selectable, including multiple data-pointers, a multiply-division unit, and a power management unit. Furthermore, the 8051 CPU can be coupled with a wide range of peripherals matching the behavior and timing of peripherals found in legacy architectures from Intel, Phillips/NXP, Siemens/Infineon, Maxim/Dallas, Texas instruments and others. Several pre-configured versions are offered; custom variations are also available.

The L8051XC1 runs legacy code, but new software development is facilitated through CAST’s on-chip debugging option, and debug pods that cooperate with IAR Embedded Workbench & Keil uVision™ IDEs.

This new product builds on CAST’s experience with hundreds of 8051 IP customers going back to 1997. Designed for easy reuse in ASICs, structured ASICs, or FPGAs, the core is strictly synchronous, with positive-edge clocking (except in the optional debug & SPI modules), synchronous reset, and no internal tri-states. Representative 40nm ASIC results show the core to be conservative in its use of space, requiring just 7,000 to 40,000 gates.

See representative implementation results (in a new pop-up window):

ASIC numbers Altera numbers Xilinx numbers

Applications

The L8051XC1 MCU core is especially effective for extending the lifetime of existing systems where an originally-used discrete 8051 chip is difficult to replace, or the designer wishes to consolidate a multi-board system into a single FPGA or ASIC.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available; contact CAST Sales.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements. All subcomponents were functionally verified with an HDL testbench using their individual test suites. The CPU and ALU have been verified against a proprietary hardware modeler and behavioral models. The peripherals have also been verified in their own testbenches, based on either hardware or behavioral models. An extensive constrained random verification was performed to verify the CPU, DMA and OCDS.

Deliverables

The core is available in ASIC (synthesizable HDL) or FPGA (netlist) forms, and includes everything required for successful implementation. ASIC versions include:

Available Versions

Three standard versions of the core are available, offering a range of capabilities and prices.

ASIC (RTL) and FPGA (netlist) deliverables are available; FPGA packages are not user-configurable.

Comparing 8051 Cores

Features

L8051XC1
Legacy

R8051XC2
Fast, Mature

T8051XC3
Tiny

S8051XC3
Super-Fast

  S80251XC3
Fast 16-bit
T80251XC3
Tiny 16-bit

Performance

DMIPS/MHz vs Original 80C51

1x, 2x or 4x

12.1x

13.5x

26.85x

  69.7x 15.4x

8x8 Multiply (Cycles)

24 or 12

4

8

1 or 2

  1 8
16x16 Multiply w/o MDU (Cycles) 50 50 67 32   1 16

16x16 Multiply with MDU (Cycles)

38

38

N/A

N/A

 

N/A

N/A

32-bit Code/Data Bus

not supported

not supported

not supported

included

  included not supported

DPTR Arithmetic Acceleration

optional

optional

optional

included

  included not supported

Advanced Execution Architecture

not supported

not supported

not supported

included

 

included

not supported

Area (eq. NAND2 Gates @180nm)

Basic CPU

5,500 - 6,800

5,500

3,500

5,300

  21,900

13,000

Memory

Program/Data Address Space

64K Bytes

64KB or 8MB

64K Bytes

64KB or 8MB

 

16M Bytes

16M Bytes

Configurable Set of Peripherals

included

included

included

included

  included

included

24-bit DPTR

not supported

not supported

not supported

not supported

  included

included

Optional Extra 16-bit DPTRs

1 to 7

1 to 7

0 to 1

0 to 1

  not supported not supported

32-bit Code/Data Bus

not supported

not supported

not supported

included

  included

not supported

Separate XDATA Bus

not supported

not supported

not supported

included

  included

not supported

Peripherals: 80C51-Like

TIMER 0 — 16-bit Counter/Timer

included

included

optional

included

  included

included

TIMER 1 — 16-bit Counter/Timer

included

included

included

included

 

included

included

SERIAL — Full duplex sync/async serial port

included

included

optional

included

 

included

included

GPIO 0 — 8-bit Paralell Port

included

included

included

included

 

included

included

GPIO 1-3 — 8-bit Paralell Ports

included

included

optional

included

 

included

included

ISR — Interrupt Controller: 6 sources and 2 priority levels

included

included

included

included

 

included

included

Peripherals: SAB80C515-Like

TIMER 2 — 16-bit Counter/ Timer/ Event Counter & Capture Compare Unit

included

included

not supported

not supported

 

not supported

not supported

WDT — 15-bit Watchdog timer

included

included

not supported

not supported

 

not supported

not supported

MDU — 32-bit Multiplication Division Unit included included optional optional   optional

optional

ISR — Interrupt Controller: 18 sources and 4 priority levels included included not supported not supported   not supported not supported
GPIO 4,5,6 — 8-bit Parallel Ports included included optional optional   optional optional
SERIAL 0 — Full duplex sync/async serial port included

included

included

included

  optional

optional

SERIAL 1 — Full duplex sync/async serial port included

included

optional

included

  optional

optional

Peripherals: Dallas 80C530-Like

RTC — Real time clock optional

included

optional

optional

  optional

optional

Peripherals: 80251Like

TIMER 2 — 16-bit Timer not supported

not supported

optional

included   included

included

WDT — 14-bit Watchdog timer optional

not supported

optional

included   included

included

PCA — Programmable Counter Array: Five 16-bit PWM optional

not supported

optional

included

  included

included

Peripherals: Proprietary

MAC — 40-bit Multiply Accumulator Unit not supported not supported not supported included   included included
PMU/DFS — Power Mgmt Unit with Dynamic Frequency Scaling not supported not supported optional included   included included
PMU — Power Mgmt Unit included included included not supported   not supported not supported
I2C 0, 1 — I2C Master/Slave with SMBUS extension included included optional included   included included
SPI_MS — SPI Master/Slave included included optional included   included included
DMA — DMA Controller optional included not supported optional   optional not supported
OCDS — On Chip Debug Support included included included included   included included
XWDT — Extended Watchdog Timer not supported optional not supported not supported   not supported not supported
ISR — Interrupt Controller: 23 sources and 4 priority levels not supported not supported optional included   included included
CAN — CAN Bus Controller optional optional optional optional   optional optional
LIN — LIN Bus Controller optional optional optional optional   optional optional
LCD — LCD/TFT Display Controller optional optional optional optional   optional optional

included= Included or user-configurable option  optional= On request  not supported= Not supported

Notes

1. Performance data correspond to maximum speed configuration
2. DMIPS/MHz for original 80C51 is 0.00941

3. Basic Peripherals: 8-bit port, Timers 0 & 1, Serial 0, PMU, ISR (INT 0–1)

 

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