- Fully compatible with the MCS® 51 instruction set
- Configurable CPU architecture: 12, 6, or 4 clock cycles per machine cycle
- Extensive set of optional features and peripherals
- JTAG-based On-Chip Debug Support (OCDS)
- Integration with IAR Embedded Workbench & Keil uVision™ IDEs
Options and Peripherals
A wide range of architectural options and peripherals is available for integration with the L8051XC1, and more peripherals can be developed on demand. The following is partial list of the off-the-shelf available peripherals:
- External Memory Interface:
- One, two or eight Data Pointers for fast data block transfer
- Additional Arithmetic Unit supports data pointers, auto-increment/-decrement, and auto-switch
- Supports external DMA controller through HOLD function
- Program memory write mode
- Direct Memory Access (DMA) Controller
- Multiplication-Division Unit
- 37 to 119 external Special Function Registers
- Interrupt Controller with two or four priority levels, and six or eighteen interrupt sources
- Up to five Parallel I/O Ports
- Serial 0 full-duplex serial interface (80C51-like), equipped with an additional baud rate generator
- Serial 1 (asynchronous-only version of Serial 0) interface
SPI Master/Slave interface
- One or two I2C™ Master/Slave interfaces
- Timers 0, 1 and Timer 2 with Compare/Capture (80C515-like)
- 15-bit programmable Watchdog Timer
- Real Time Clock
- Power Management Unit with power-down modes (IDLE/STOP)
Contact Sales
Call or click.
+1 201.391.8300
Downloads (PDFs)
Related Products
The 8051 family also includes:
- R8051XC2 High-Performance, Configurable, 8051-Compatible, 8-bit Microcontroller IP Core
- S8051XC3 Super-Fast 8051 Microcontroller IP Core with Configurable Features and Peripherals
- T8051XC3 Ultra-Small 8051-Compatible Microcontroller IP Core
- S80251XC3 Super-fast, Configurable 16-bit 80251-compatible Microcontroller IP Core
- T80251XC3 Tiny, Configurable, 16-bit 80251-compatible Microcontroller IP Core
Download our Controllers & Processors IP Overview (PDF).
Development Tools & Options
Coding and debug this 8051 with these popular IDEs:
These tools work with an optional, native on-chip debug block and inexpensive external adapter (pod) with a JTAG four-wire or SWAT Single-Wire PC interface.
Evaluation:
Try it for Yourself
Easily evaluate this 8051's features and performance in your own environment with the Talos Series Evaluation Kit.
Articles
Understanding Interrupt Latency in Modern 8051s by Nikos Zervas at ChipEstimate.com
CAST Announces World's Fastest 8051-Compatible MCU Core by Max Maxfield, EE Times
CAST’s 8051 IP core is going strong
Article by Clive Maxwell, EE Times
Using 8-bit 8051s in a 32-bit World
Article by Bill FInch, in Extension Media's Engineers' Guide to 8/16-bit Technologies
Blog Posts
- Webinar: Easier Development for Today's 8051 MCUs with IAR Embedded Workbench for 8051
- IAR Systems 8051 Partnership Brings High-Productivity Design and Debug Tools to 8051 Developers
- Gabrielle Saucier Interviews Hal Barbour at D&R IP SoC Grenoble 2014
See more 8051 blog posts >>>
L8051XC1Legacy-Configurable 8051-Compatible Microcontroller IP Core
The L8051XC1 core implements an MCS®51-compatible microcontroller that is specially designed to match the timing and peripherals of legacy 8051 MCU based systems.
The core can be configured to execute an instruction every 12, 6, or 4 clock cycles. Architectural extensions are user-selectable, including multiple data-pointers, a multiply-division unit, and a power management unit. Furthermore, the 8051 CPU can be coupled with a wide range of peripherals matching the behavior and timing of peripherals found in legacy architectures from Intel, Phillips/NXP, Siemens/Infineon, Maxim/Dallas, Texas instruments and others. Several pre-configured versions are offered; custom variations are also available.
The L8051XC1 runs legacy code, but new software development is facilitated through CAST’s on-chip debugging option, and debug pods that cooperate with IAR Embedded Workbench & Keil uVision™ IDEs.
This new product builds on CAST’s experience with hundreds of 8051 IP customers going back to 1997. Designed for easy reuse in ASICs, structured ASICs, or FPGAs, the core is strictly synchronous, with positive-edge clocking (except in the optional debug & SPI modules), synchronous reset, and no internal tri-states. Representative 40nm ASIC results show the core to be conservative in its use of space, requiring just 7,000 to 40,000 gates.
This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements. Meanwhile, we provide the following representative results (each in a new pop-up window):
Applications
The L8051XC1 MCU core is especially effective for extending the lifetime of existing systems where an originally-used discrete 8051 chip is difficult to replace, or the designer wishes to consolidate a multi-board system into a single FPGA or ASIC.
Support
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available; contact CAST Sales.
Verification
The core has been verified through extensive simulation and rigorous code coverage measurements. All subcomponents were functionally verified with an HDL testbench using their individual test suites. The CPU and ALU have been verified against a proprietary hardware modeler and behavioral models. The peripherals have also been verified in their own testbenches, based on either hardware or behavioral models. An extensive constrained random verification was performed to verify the CPU, DMA and OCDS.
Deliverables
The core is available in ASIC (synthesizable HDL) or FPGA (netlist) forms, and includes everything required for successful implementation. ASIC versions include:
- HDL RTL source code
- Easy-to-use configuration tool (with configurable versions)
- An example chip implementation, which uses the core in a sample system
- Sophisticated self-checking HDL Testbench including everything needed to test the core (Verilog versions use Verilog 2001)
- Simulation script, vectors, and expected results
- Synthesis script
- Comprehensive user documentation, including detailed specifications and a system integration guide
Available Versions
Three standard versions of the core are available, offering a range of capabilities and prices.
- L8051XC1-A includes options that match the original Intel 8051 peripheral set: 64KB memory interface, two timers, one serial port, four parallel I/O Ports, two-level interrupt controller, and two DPTR registers. These options are user-configurable (i.e., may be deleted prior to synthesis).
- L8051XC1-B includes options that match the Infineon 80515/80517 peripheral set: 64KB memory interface, three timers, two serial ports, four parallel I/O ports, watchdog timer, multiplication-division unit, and two DPTR registers. These options are user-configurable (i.e., may be deleted prior to synthesis).
- L8051XC1-C custom/user-defined architectural and peripheral options. This version may integrate user-defined peripherals that are not supported by the automatic configuration tool. Please consult with your CAST sales contact to discuss your specific requirements and get lead time information
ASIC (RTL) and FPGA (netlist) deliverables are available; FPGA packages are not user-configurable.
Comparing 8051 Cores
Features |
S80251XC3 Fast 16-bit |
T80251XC3 Tiny 16-bit |
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Performance |
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DMIPS/MHz vs Original 80C51 |
1x, 2x or 4x |
12.1x |
13.5x | 26.85x |
69.7x | 15.4x | |
8x8 Multiply (Cycles) |
24 or 12 |
4 |
8 |
1 or 2 |
1 | 8 | |
16x16 Multiply w/o MDU (Cycles) | 50 | 50 | 67 | 32 | 1 | 16 | |
16x16 Multiply with MDU (Cycles) |
38 |
38 |
N/A |
N/A |
N/A |
N/A |
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32-bit Code/Data Bus |
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DPTR Arithmetic Acceleration |
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Advanced Execution Architecture |
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Area (eq. NAND2 Gates @180nm) |
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Basic CPU | 5,500 - 6,800 |
5,500 |
3,500 |
5,300 |
21,900 | 13,000 |
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Memory |
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Program/Data Address Space |
64K Bytes |
64KB or 8MB |
64K Bytes |
64KB or 8MB |
16M Bytes |
16M Bytes |
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Configurable Set of Peripherals |
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24-bit DPTR |
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Optional Extra 16-bit DPTRs |
1 to 7 |
1 to 7 |
0 to 1 |
0 to 1 |
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32-bit Code/Data Bus |
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Separate XDATA Bus |
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Peripherals: 80C51-Like |
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TIMER 0 — 16-bit Counter/Timer |
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TIMER 1 — 16-bit Counter/Timer |
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SERIAL — Full duplex sync/async serial port |
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GPIO 0 — 8-bit Paralell Port | |||||||
GPIO 1-3 — 8-bit Paralell Ports | |||||||
ISR — Interrupt Controller: 6 sources and 2 priority levels | |||||||
Peripherals: SAB80C515-Like |
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TIMER 2 — 16-bit Counter/ Timer/ Event Counter & Capture Compare Unit | |||||||
WDT — 15-bit Watchdog timer | |||||||
MDU — 32-bit Multiplication Division Unit | ![]() |
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ISR — Interrupt Controller: 18 sources and 4 priority levels | ![]() |
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GPIO 4,5,6 — 8-bit Parallel Ports | ![]() |
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SERIAL 0 — Full duplex sync/async serial port | ![]() |
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SERIAL 1 — Full duplex sync/async serial port | ![]() |
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Peripherals: Dallas 80C530-Like |
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RTC — Real time clock | ![]() |
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Peripherals: 80251Like |
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TIMER 2 — 16-bit Timer | ![]() |
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WDT — 14-bit Watchdog timer | ![]() |
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PCA — Programmable Counter Array: Five 16-bit PWM | ![]() |
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Peripherals: Proprietary |
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MAC — 40-bit Multiply Accumulator Unit | ![]() |
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PMU/DFS — Power Mgmt Unit with Dynamic Frequency Scaling | ![]() |
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PMU — Power Mgmt Unit | ![]() |
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I2C 0, 1 — I2C Master/Slave with SMBUS extension | ![]() |
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SPI_MS — SPI Master/Slave | ![]() |
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DMA — DMA Controller | ![]() |
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OCDS — On Chip Debug Support | ![]() |
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XWDT — Extended Watchdog Timer | ![]() |
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ISR — Interrupt Controller: 23 sources and 4 priority levels | ![]() |
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CAN — CAN Bus Controller | ![]() |
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LIN — LIN Bus Controller | ![]() |
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LCD — LCD/TFT Display Controller | ![]() |
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Notes 1. Performance data correspond to maximum speed configuration 3. Basic Peripherals: 8-bit port, Timers 0 & 1, Serial 0, PMU, ISR (INT 0–1) |