L8051XC1Legacy-Configurable 8051-Compatible Microcontroller IP Core

The L8051XC1 core implements an MCS®51-compatible microcontroller that is specially designed to match the timing and peripherals of legacy 8051 MCU based systems.

The core can be configured to execute an instruction every 12, 6, or 4 clock cycles. Architectural extensions are user-selectable, including multiple data-pointers, a multiply-division unit, and a power management unit. Furthermore, the 8051 CPU can be coupled with a wide range of peripherals matching the behavior and timing of peripherals found in legacy architectures from Intel, Phillips/NXP, Siemens/Infineon, Maxim/Dallas, Texas instruments and others. Several pre-configured versions are offered; custom variations are also available.

The L8051XC1 runs legacy code, but new software development is facilitated through CAST’s on-chip debugging option, and debug pods that cooperate with IAR Embedded Workbench & Keil uVision™ IDEs.

This new product builds on CAST’s experience with hundreds of 8051 IP customers going back to 1997. Designed for easy reuse in ASICs, structured ASICs, or FPGAs, the core is strictly synchronous, with positive-edge clocking (except in the optional debug & SPI modules), synchronous reset, and no internal tri-states. Representative 40nm ASIC results show the core to be conservative in its use of space, requiring just 7,000 to 40,000 gates.

This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements. Meanwhile, we provide the following representative results (each in a new pop-up window):

Applications

The L8051XC1 MCU core is especially effective for extending the lifetime of existing systems where an originally-used discrete 8051 chip is difficult to replace, or the designer wishes to consolidate a multi-board system into a single FPGA or ASIC.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available; contact CAST Sales.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements. All subcomponents were functionally verified with an HDL testbench using their individual test suites. The CPU and ALU have been verified against a proprietary hardware modeler and behavioral models. The peripherals have also been verified in their own testbenches, based on either hardware or behavioral models. An extensive constrained random verification was performed to verify the CPU, DMA and OCDS.

Deliverables

The core is available in ASIC (synthesizable HDL) or FPGA (netlist) forms, and includes everything required for successful implementation. ASIC versions include:

• HDL RTL source code
• Easy-to-use configuration tool (with configurable versions)
• An example chip implementation, which uses the core in a sample system
• Sophisticated self-checking HDL Testbench including everything needed to test the core (Verilog versions use Verilog 2001)
• Simulation script, vectors, and expected results
• Synthesis script
• Comprehensive user documentation, including detailed specifications and a system integration guide

Available Versions

Three standard versions of the core are available, offering a range of capabilities and prices.

• L8051XC1-A includes options that match the original Intel 8051 peripheral set: 64KB memory interface, two timers, one serial port, four parallel I/O Ports, two-level interrupt controller, and two DPTR registers. These options are user-configurable (i.e., may be deleted prior to synthesis).
• L8051XC1-B includes options that match the Infineon 80515/80517 peripheral set: 64KB memory interface, three timers, two serial ports, four parallel I/O ports, watchdog timer, multiplication-division unit, and two DPTR registers. These options are user-configurable (i.e., may be deleted prior to synthesis).
• L8051XC1-C custom/user-defined architectural and peripheral options. This version may integrate user-defined peripherals that are not supported by the automatic configuration tool. Please consult with your CAST sales contact to discuss your specific requirements and get lead time information

ASIC (RTL) and FPGA (netlist) deliverables are available; FPGA packages are not user-configurable.

Comparing 8051 Cores

Features	L8051XC1 Legacy	R8051XC2 Fast, Mature	T8051XC3 Tiny	S8051XC3 Super-Fast		S80251XC3 Fast 16-bit	T80251XC3 Tiny 16-bit
Performance
DMIPS/MHz vs Original 80C51	1x, 2x or 4x	12.1x	13.5x	26.85x		69.7x	15.4x
8x8 Multiply (Cycles)	24 or 12	4	8	1 or 2		1	8
16x16 Multiply w/o MDU (Cycles)	50	50	67	32		1	16
16x16 Multiply with MDU (Cycles)	38	38	N/A	N/A		N/A	N/A
32-bit Code/Data Bus
DPTR Arithmetic Acceleration
Advanced Execution Architecture
Area (eq. NAND2 Gates @180nm)
Basic CPU	5,500 - 6,800	5,500	3,500	5,300		21,900	13,000
Memory
Program/Data Address Space	64K Bytes	64KB or 8MB	64K Bytes	64KB or 8MB		16M Bytes	16M Bytes
Configurable Set of Peripherals
24-bit DPTR
Optional Extra 16-bit DPTRs	1 to 7	1 to 7	0 to 1	0 to 1
32-bit Code/Data Bus
Separate XDATA Bus
Peripherals: 80C51-Like
TIMER 0 — 16-bit Counter/Timer
TIMER 1 — 16-bit Counter/Timer
SERIAL — Full duplex sync/async serial port
GPIO 0 — 8-bit Paralell Port
GPIO 1-3 — 8-bit Paralell Ports
ISR — Interrupt Controller: 6 sources and 2 priority levels
Peripherals: SAB80C515-Like
TIMER 2 — 16-bit Counter/ Timer/ Event Counter & Capture Compare Unit
WDT — 15-bit Watchdog timer
MDU — 32-bit Multiplication Division Unit
ISR — Interrupt Controller: 18 sources and 4 priority levels
GPIO 4,5,6 — 8-bit Parallel Ports
SERIAL 0 — Full duplex sync/async serial port
SERIAL 1 — Full duplex sync/async serial port
Peripherals: Dallas 80C530-Like
RTC — Real time clock
Peripherals: 80251Like
TIMER 2 — 16-bit Timer
WDT — 14-bit Watchdog timer
PCA — Programmable Counter Array: Five 16-bit PWM
Peripherals: Proprietary
MAC — 40-bit Multiply Accumulator Unit
PMU/DFS — Power Mgmt Unit with Dynamic Frequency Scaling
PMU — Power Mgmt Unit
I2C 0, 1 — I2C Master/Slave with SMBUS extension
SPI_MS — SPI Master/Slave
DMA — DMA Controller
OCDS — On Chip Debug Support
XWDT — Extended Watchdog Timer
ISR — Interrupt Controller: 23 sources and 4 priority levels
CAN — CAN Bus Controller
LIN — LIN Bus Controller
LCD — LCD/TFT Display Controller
= Included or user-configurable option  = On request  = Not supported Notes 1. Performance data correspond to maximum speed configuration 2. DMIPS/MHz for original 80C51 is 0.00941 3. Basic Peripherals: 8-bit port, Timers 0 & 1, Serial 0, PMU, ISR (INT 0–1)