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VGA-CTRL Video Display Controller Core

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | Example Application | Support | Verification | Deliverables

Implements a controller that accepts video data and works with a digital/analog converter (DAC) to drive standard VGA and SVGA displays.

The core’s system interface uses the AMBA AHB bus. It accepts two different standard input formats — 15-bit (5:5:5) and 24-bit (8:8:8) RGB — and produces 24-bit RGB pixel data. It also generates all of the required horizontal and vertical timing periods: horizontal and vertical front porch, back porch and sync intervals. Video aspect ratios and monitor frequencies are configurable, and various display functions are provided.

The core passes 24-bit RGB to standard analog/digital video converters such as Analog Devices’ ADV7120 CMOS, 80MHz, Triple 8-Bit Video DAC (ADV®). The DAC then generates output signals compatible with RS-343A/RS-170 standards.

Test and power save modes are built into the core. The design is strictly synchronous with positive-edge clocking, no internal tri-states and asynchronous reset; therefore scan insertion is straightforward. ASIC implementation results show it to require about 11,000 gates.

See representative implementation results (each in a new pop-up window):

Features

• Generates color and control data for standard VGA/SVGA displays
• Works in conjunction with external video DAC such as Analog Devices’ ADV7120
• Supports resolution up to 1024 x 1024 (higher resolutions available upon request)
• Accepts two standard video data formats:
• 24-bit RBG (8:8:8)
• 15-bit RBG (5:5:5)
• Outputs standard 8:8:8 24-bit RGB video (converts from 5:5:5 if necessary)
• Display functions with hardware support:
• Scroll (in horizontal and vertical directions)
• Sub-screen display (any position)
• Horizontal flip screen
• Fully configurable monitor frequencies and aspect ratios
• 32-bit data path
• Configurable internal FIFO
• Integrated Test mode: core generates color bar without any AHB bus transactions
• Internal, event-stimulated, interrupt request generation with masking capability
• Dedicated unidirectional DMA controller with burst transaction support
• Built-in Power Save mode
• Requires an external pixel clock.
• Integrated with AMBA™ bus:
• AMBA™ AHB slave unit interfaces with host controller
• AMBA™ AHB master unit interfaces with host memory

Applications

The core is designed to work with a video data processor as Analog Devices ADV7120 Video DAC in a variety of video display systems, including

• Portable video systems
• Digital cameras with video output
• Advanced mobile phones with video capabilities

Block Diagram

Functional Description

The core combines a flexible VGA data generation module with additional elements necessary to communicate with its host system, accept and convert different forms of video data, and store that data for processing and output.

AMBA AHB Master & Slave

The core operates as a master device for data transfers, so the AHB Master wrapper implements master AHB signals and functions. The core acts as a slave for register opera-tions, and so uses the AHB Slave wrapper implementation.

VGA

A fully-configurable display controller, adapted to handle the Analog Devices’ ADV7120 - CMOS, 80MHz, Triple 8-Bit Video DAC (or similar device). It takes input data in 24-bit parallel format and outputs this data with composite synchronization and video blanking signals. It generates all the required horizontal and vertical timing periods: horizontal and vertical front porch, back porch, and sync intervals.

DMA

Takes pixel data from the AHB wrapper, converts it from the two possible pixel formats (RGB 24-bits/pixel and RGB 15-bits/pixel) as necessary (in the CONV module) for the VGA, and stores the data in a FIFO buffer. It also generates data in test mode without any AHB bus activity.

FIFO

Buffers pixel data between the CONV and VGA units and works in two clock domains. Its size is parameterized, and it cooperates with off-chip dual port memory.

Example Application

Here the core is used to send data from system memory to a hard disk drive. It uses the DMA Interface, and the CPU processes interrupts and controls the settings.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core’s functionality was verified by processing bitmap pictures. These were converted by a C program into stimuli and reference files. The stimuli files were applied to core inputs, and the reference files compared with the core simulation outputs.

The VGA-CTRL has also been verified through extensive functional simulation and it has achieved high Code Coverage results. A demo system has been implemented.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• An example implementation with sample system
• Sophisticated self-checking HDL Testbench including everything needed to test the core
• Simulation scripts, vectors, and expected results
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | Example Application | Support | Verification | Deliverables

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This core developed by the peripheral controller experts at Evatronix SA