PDF datasheets: ASIC Altera Xilinx Related information: News Release 03/07/05 CAST Expands USB OTG Line with New Multi-Port IP Core Resources For an excellent USB overview, see Which version of USB is right for your application?, by Dan Harmon, at Planet Analog For more information: Contact Sales @ CAST Certification: This core has received USB-IF certification (through development partner Evatronix).

USBHS-OTG-MPD USB Hi-Speed On-The-Go Controller for Multiple Peripheral Devices Core

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | Support | Verification | Deliverables

The USBHS-OTG-MPD core implements a hi-speed USB port that can serve as either a host or a peripheral when connected to other USB devices. It features an integrated direct memory access (DMA) controller for efficient, autonomous data transfer, and can support USB hubs and multiple peripheral devices in host mode.

The core’s dual-role behavior conforms to the On-The-Go Supplement to the USB 2.0 specification. The core is designed for processing efficiency, with hardware state ma-chines implementing the Host Negotiation Protocol, Session Request Protocol, and other critical functions, and is competitive in both performance and area usage.

Standard USB transceivers can be used through the core's UTMI+ interface. The core's system connection is an AMBA™ AHB slave interface (other standard interfaces are also available). The number and qualities of up to 15 configurable endpoints and other USB characteristics can be customized prior to synthesis to match the core to a specific application, and the core supports USB power saving functions.

The USBHS-OTG-MPD is a testable, microcode-free design developed for reuse in ASICs and FPGAs. A complete test environment helps designers verify the functioning and compliance of the core, and includes a behavioral model of the PHY software layer to allow easy transaction simulation.

See representative implementation results (each in a new pop-up window):

Features

• Complies with the USB 2.0 specification and On-The-Go supplement to the USB 2.0 specification
• In Host Mode, supports Hi-Speed hubs and multiple Low-Speed, Full-Speed or Hi-Speed peripheral devices
• In Device Mode, supports Full-Speed and Hi-Speed data transfer
• Supports USB split transactions
• Support for Host Negotiation Protocol and Session Request Protocol (in hardware)
• Control transfers supported by Endpoint 0
• UTMI+ (Level3) or ULPI Transceiver Macrocell Interface
• 32-bit AMBA™ AHB slave interface
• Integrated multichannel DMA module
• 32-bit AMBA™ AHB master interface
• USB protocol-aware DMA engine
• Synchronous RAM interface for endpoint FIFOs
• Suspend and resume power managements functions
• Remote Wake-Up function
• Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)

Configurability

• Configurable for up to 15 IN and 15 OUT endpoints
• Configurable/programmable number of endpoints
• Programmable type of endpoints (bulk, ISO, interrupt)
• Programmable TX FIFO size and RX FIFO size

Applications

Enables the direct connection of digital products without a computer host, for example:

• Connecting a digital camera directly to a printer for prints or to a cellular phone for Internet photo sharing
• Connecting a digital music player to a CD player to download songs, to a set of speakers to play them, and to a disk burner to archive custom playlists
• Connecting a PDA to a flash memory drive for backing up data, to a logic analyzer for transferring lab results, or to another PDA for file sharing

Block Diagram

Functional Description

The core is partitioned into modules as shown on the block diagram and described below.

OTG Controller

Supports all tasks specified in the OTG supplement and implements the downstream and upstream ports. Also provides the hardware implementation of the HNP (Host Negotiation Protocol) and SRP (Session Request Protocol). The SFRS block controls the HNP and SRP.

The dual-role core can act as a USB host or a USB periph-eral device. An id-input pin controls the default role: if id=1 it means a mini-B plug was connected and the core becomes a B-device (peripheral), and when id=0 it means a mini-A plug was connected and the core becomes an A-device (host).

UTMI+ Interface

The core requires an external transceiver that is compatible with the USB 2.0 UTMI+ specification (Philips USB 2.0 Transceiver Macrocell Interface Plus, version 1.0).

Endpoints Logic

Coordinates use of the same endpoint resources in host and peripheral modes. It is fully configurable: the number of end-points, and the size of the transmit and receive FIFOs can be adjusted to achieve a specific implementation.

SFRS

A set of Special Function Registers used to control the core’s operation.

Host Controller

Functions when the core works as a USB host. Its main tasks are:

• Generation of suspend/resume signaling and USB reset
• Generation of SOF tokens
• USB data transactions
• Generation of host interrupts

It also contains the Host Transaction Scheduler (HTS), which analyzes how many endpoints wait for service and decides which endpoints will be serviced in the current (m)frame and which in the next (m)frame.

Device Controller

Implements the tasks of a USB device:

• USB data transactions
• Suspend/resume behavior
• Generation of interrupts

Application Interface

Contains the interrupt controller, which generates interrupt signals for microprocessor, and the 32-bit AMBA™ AHB slave interface.

DMA Controller

Controls data transfer between the endpoints buffers and system memory.

• 32-bit AMBA™ AHB master interface
• Multichannel DMA
• Interrupt request after USB transfer (multiple USB transactions) is completed

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation using a large set of test vectors and reference results, and through rigorous code coverage measurements.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation. The ASIC version includes:

• HDL RTL source code
• An example chip implementation, which uses the core in a sample system.
• Sophisticated self-checking Testbench (Verilog versions use Verilog 2001) including external endpoint buffers, a bus/behavioral model USB stimulator (PHY), and a clock generator
• Simulation scripts, vectors, and expected results
• Synthesis script
• Comprehensive user documentation, including detailed specifications and a system integration guide

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | Support | Verification | Deliverables

Download PDF datasheets for more info: ASIC | Altera | Xilinx

This core developed by the bus interface experts at Evatronix SA